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TMS570LC4357: Flash/RAM swap

Alex Spivak
Intellectual 930 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: TMS570LS3137

Hello,

We are switching our software from TMS570LS3137 to  TMS570LC4357 and it seems that TMS570LC4357 is not behaving right when Flash and Ram are swapped by setting the key in BMMCR1 register. We have a software that is used to load software updates to Flash and this software runs from RAM (to be able to access Flash). The software is placed in the Flash and when used it is copied into RAM (address 0x08000000) and at that point BMMCR1.MEMSW field is set to 5. After this is done the RAM that contained the previously copied software gets cleared in random locations (blocks). This was not happening with TMS570LS3137, although we were not using MPU at that time. Is it related to the MPU that we are using now? This problem occurs even if the MPU is disabled before the memory swap.

Additional issue that I observe is with the CPURSTCR register. The TRM is sais that the CPU RESET bit needs to be toggled for the CPU reset, but the reset doesn't happen if the bit was 1 and is set to 0. Also this bit is not cleared after System Reset. Is that a normal behavior? 

Thanks,

Alex

  • 0
    TI__Guru**** 198766 points

    Hello,

    How do you swap the memory?

    Swap SRAM and flash:

    *(int *) 0xffffffc4 = 0x05050505;
    *(int *) 0xffffffcc = 0x00000001;
    *(int *) 0xffffffcc = 0x00000000;

    For TMS5670LC43x device, after the memory swap, the SRAM should be cleared to prevent the ECC error:

    *(int *) 0xffffff5c = 0x0000000a;
    *(int *) 0xffffff60 = 0xffffffff;
    *(int *) 0xffffff5c = 0x00000005;

  • 0 in reply to QJ Wang
    Intellectual 930 points

    Hi Wang,

    I'm a little confused with your response.

    Why do you write 0x05050505 to 0xfffffffc and not just 0x00000005? Per the TRM only the lower 4 bits are available for the key value and the rest are reserved.

    After "*(int *) 0xffffffcc = 0x00000001;" is done the CPU is reset, so how the next assignment "*(int *) 0xffffffcc = 0x00000000;" will be executed?

    You are saying "For TMS570LC43x device, after the memory swap, the SRAM should be cleared to prevent the ECC error", but after the memory swap and reset, the CPU begins to execute instructions from RAM, so why would you clear the SRAM that the CPU is running from? Why the ECC error needs to be cleared if the ECC RAM locations are also swapped and preserved?

    What is the intent of having Flash and RAM swap on the Hercules processors?

    Here is what we want to do (we were doing it on TM570LS3137 processor):

    1. Copy program from Flash to SRAM location 0x08000000.
    2. Swap Flash and SRAM
    3. Reset the CPU
    4. CPU is now running the program located in SRAM, which is able to perform loading binary data and flashing it into any Flash location.

    Can we do that with TMS570LC43x device?

    Thanks,

    Alex

  • 0 in reply to Alex Spivak
    TI__Guru**** 198766 points

    Hello Alex,

    1. You are right. Only bit [3:0] of BMMCR register is used. Writing to [31:4] have no effect. 

        *(int *) 0xffffffc4 = 0x00000005; 

    2.  *(int *) 0xffffffcc = 0x00000001;
         *(int *) 0xffffffcc = 0x00000000;

         A CPU reset is initiated by changing the state of the bit 0 (CPU RESET) in the CPURSTCR register.

  • 0 in reply to QJ Wang
    TI__Guru**** 198766 points

    Hello Alex,

    Loading code to SRAM is faster, and it doesn't consume the flash (max write/erase cycles is 1000 cycles). 

    Please refer to this thread for loading code to RAM and execute code from RAM.

    https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/147475/533475?tisearch=e2e-sitesearch&keymatch=memory%25252520swap#533475

  • 0 in reply to QJ Wang
    Intellectual 930 points

    Hi Wang,

    I see that the main purpose of running from RAM is for faster debugging. We didn't use it that way. Loading to Flash was fast enough and we didn't notice flash errors yet. However, I can see that we cannot do on TMS570LC43x what we did on  TM570LS3137, because I see that in spnu563a section 2.2.1 the note sais that after the memory swap the flash can be accessed up to the size of the RAM (512K), while in spnu499c same section, this note doesn't exist. I guess I will have to find a different solution running from RAM to be able to modify most of the Flash without swapping RAM and Flash.