Other Parts Discussed in Thread: TM4C123GH6PM
Hello:
We are looking into the best way to have multiple slave devices on a same SPI interface in the Tiva C series. Can some GPIO lines be used as chip select lines (and asserted independently before the start of the SPI transfer) independently of the SSixFss line of each interface? If this is possible, which will be the state of the SSIxFss line when the SPIx interface transfer is active?
Any help, hits and suggestions will be really appreciated!
Dario