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CCS/LAUNCHXL2-TMS57012: SPI issue

Sam S1
Prodigy 120 points
Part Number: LAUNCHXL2-TMS57012
Other Parts Discussed in Thread: TMS570LS1224

Tool/software: Code Composer Studio

I am using MibSPI1 port on TMS570LS1224, I came across two SIMO and SOMI pins for the same MibSPI port. Why So? please explain.

Example:-

 MIBSPI1SIMO[0] -> F19

 MIBSPI1SIMO[1] ->  E18

Why there are multiple SIMO/SOMI pins for the same MIBSPI1 port? Also can we use both?

And  There are multiple number of SOMI and SIMO pins for MIBSPI5, Why?

Example:-

MIBSPI5SIMO[1]-> E16

MIBSPI5SIMO[2]-> H17

MIBSPI5SIMO[3]-> G17

MIBSPI5SOMI[0]-> J18

MIBSPI5SOMI[1]-> E17

Please explain this architecture.

Also, please provide example code to test SPI functionality.

  • 0
    TI__Guru**** 196566 points

    Hello,

    TMS570LS1224 microcontroller supports multi-pin parallel mode. The parallel mode enables the module to send data over more than one data line  to increase the throughput. 

    The throughput is increased by 2 for 2 pins, by 4 for 4 pins.

    In 2-data line mode, the shift register bits 15 and 7 are connected to the pns SIMO[1] and SIMO[0], and shift register bits 8 and 0 are connected to pins SOMI[1] and SOMI[0]. After writing to the SPIDAT0/SPIDAT1 register, the bits 15 and 7 will be output on SIMO[1] and SIMO[0] on the rising edge if SPICLK. With the falling clock edge of the SPICLK, the received data on SOMI[1] and SOMI[0] will be latched to the shift register bits 8 and 0.

  • 0 in reply to QJ Wang
    TI__Guru**** 196566 points

    You will find the example code in this application note:

    http://www.ti.com/lit/an/spna231/spna231.pdf