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Original question:

TMS570LS0432: Master-Slave SPI communication

TMS570LS1224: SPI Transmit data corrupted !

Suresh Jayagondar1
Prodigy 220 points
Part Number: TMS570LS1224

Hi,

I am using the project SPI_MASTER_TMS570LS1224PGE, refereed in the problem in below link

On a button press i was able to send data, but having a strange problem of data not been sent out correctly, some of data is miss interpreted cos of the clock is not in sync. Below are some of the snapshots from logic analyzer 
Transmit data is 
uint16 TX_Data_Master[16] = { 0x05, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10 }; Last three bytes are corrupted( this pattern is random, some times its different bytes)
After Zooming in on one of the bytes which is corrupted, looks like data and clock are not in sync, below is the snapshot. I am not sure what is causing this, need some help
  • 0
    TI__Guru**** 197036 points

    Hello Suresh,

    The last three bytes of MOSI in the snapshot are correct. They are 0x0E, 0x0F and 0x10 rather than 0x06, 0x07 and 0x00.

    For clock phase=0, the minimum delay time (SPI_SIMO valid before SPICLK low)  is 0.5*tC - 6 (ns). The delay in your 2nd snapshot is 0.5*tC - 4ns which is the valid range.

  • 0 in reply to QJ Wang
    Prodigy 220 points

    Hi QJ Wang,

    Thanks for the Quick reply, When i decoded manually i also saw that Waveform indicates correct data. But logic analyzer did not read it correctly.

    I do not have slave connected to the master yet, i was just checking data on scope. From what your reply can I interpret as when i have slave connected it will get correct data because delay is in valid range ?

  • 0 in reply to Suresh Jayagondar1
    TI__Guru**** 197036 points

    Yes, the SPI slave should read the correct data. One slave side, data is latched on the falling edge of SPICLK. Your logic analyzer may be configured to capture data at rising edge of SPICLK.