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Original question:

Question about MIBSPI slave mode [TMS570LS3137]

TMS570LC4357: MiBSPI in multi-buffer, slave mode, to hold ENA

Jia Zhi Lim
Prodigy 150 points
Part Number: TMS570LC4357

Hi,

I am trying MiBSPI, I am using MIBSPI1 as master and MIBSPI3 as slave on TMS570LCHDK.

Both module are configured in five-pin mode(using CLK, ENA, CS0, SIMO, SOMI). Data sending between both modules(using TXRAM, RXRAM and TG0) are working.

My slave would like to receive some command from master, hold ENA high and process the command, then only response via SPI by writing to TXDATA. Then the master will just require single transfer to send command and receive the response. In the end, the MibSPI master and slave will run on two separate TMS570LC4357.

I tried changing BUFMODE to suspend single-transfer mode in the slave, but the ENA signal will still be asserted even if TXFULL=0 on that buffer.

Trying changing BUFMODE to suspend single-transfer mode in master, SPI will stop transmitting when reached buffer with TXFULL=0.

Is it possible to let slave hold ENA high but using BUFMODE in suspend single-transfer mode until TXDATA is updated?

If not, is there anyway to let slave hold ENA high? 

  • 0
    TI__Guru**** 197006 points

    The nSPIENA is HIGH by default when it is in functional mode. It is driven to LOW when new data is written to SPIDAT1 and the slave is selected by the master (nCS is LOW). If the nCS is HIGH, the slave SPIENA is driven HIGH.

    The nSPIENA is driven to HIGH once SPI completes receiving a new word. The SPI will drive nSPIENA LOW again for next word after new data is written to the slave SPIDAT1 register.

  • 0 in reply to QJ Wang
    Prodigy 150 points

    Hi QJ Wang, thank you for the reply.

    But is there a way to stop MibSPI slave to write to SPIDAT1 register(hence keeping nSPIENA HIGH) until a valid data is written to TXRAM?

    My understanding is setting BUFMODE to 5h(suspend single-transfer mode) should stop MibSPI slave to stop writing to SPIDAT1 until TXFULL flag is set(new data is written to TXRAM.data). Is my understanding correct? I tried the BUFMODE setting and MibSPI slave continue to drive nSPIENA LOW and output when TXFULL flag is not set.

    Regards,

    Jia Zhi

  • 0 in reply to QJ Wang
    Prodigy 150 points

    Hi,

    Is there any update? My question is:

    1. Will setting BUFMODE in TXRAM of slave MibSPI in Multi-buffered mode, cause the sequencer to suspend?

    *I tested on hardware that sequencer can be suspended in Master mode with BUFMODE configuration, but cannot be suspended in Slave mode, but TRM didnt state that it only work in Master mode

    2. Is there any other way for MibSPI slave to stop receiving(stop asserting SPIENA) automatically after one transfer group receive, until it's enabled again by software, making it like oneshot mode?

  • 0 in reply to Jia Zhi Lim
    TI__Guru**** 197006 points

    Hello JiaZhi,

    Sorry for late response. 

    1. Can you try BUFMODE=6: Suspend-to-wait until the corresponding RXEMPTY flag is set ?

    2. Another way, you can configure SPIENA as GIO in slave side, then pull-high or pull-low manually. SPIENA in master side should be SPI functional pin.

  • 0 in reply to QJ Wang
    TI__Guru**** 197006 points

    Hello JiaZhi,

    BufMode settings do not affect the SPIENA. In multi-buffered mode, the SPIENA is asserted when the FSM sequencer transfers data from TX RAM to TX shift register (meanwhile the received data is copying to RX RAM), the SPIENA is deasserted between 2 buffers transactions.