Hi there,
With a standard SPI module configured as a slave, and DMA configured to transfer received data from that module, could I please confirm:
1) if more clock edges are received than expected via CHARLEN, between CS asserting & deasserting, DLENERRFLG will be set?
2) if fewer clock edges are received than expected via CHARLEN, between CS asserting & deasserting, DLENERRFLG will be set?
3) it is the role of the Software to query & respond to DLENERRFLG - (the DMA will not & can not "flush" the receive buffer following an error)?
With thanks, Mark