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TMS570LS1114: DMA and CPU bus arbitration

Arshad moilingal
Prodigy 200 points
Part Number: TMS570LS1114


Hello,

What would happen when CPU is copying 8 bytes of data from SRAM to SRAM (different source and destination address), while doing so, DMA HW transfer initiated by CAN to DMA to copy the data from CAN register space to same source address in which CPU is doing copying action.

  • 0
    TI__Guru**** 198766 points

    Hello Arshad,

    1. If SW DMA request and CAN DMA request use the same DMA channel, the CAN DMA request will be captured into the request buffer, serviced after SW DMA request is complete.

    2. If they use different channel, the request mapped to lower DMA channel has higher priority. If the DMA channel (for example CH0) for SW request is lower than CAN DMA request (for example CH5), the DCAN DMA request at CH5 will not be serviced until the SW request at CH0 is completed.

    If the channel for SW request (for example CH5) is higher than DCAN request (CH0), when DCAN DMA request is trigger, the SW DMA at CH5 will be arbitrated out until the DCAN DMA request is done.

  • 0 in reply to QJ Wang
    Prodigy 200 points

    Hello QJ wang,

    I think you had interrupted my question in a wrong way. Your explanation is clear about SW DMA and HW DMA. But, this answer does not fit to the question that asked. I will try once again to explain the question once again.

     

    What would happen when CPU is copying 8 bytes of data from SRAM to SRAM (different source address and destination address) using CPU memory copy function without DMA SW request, while doing so, DMA HW transfer initiated by CAN to DMA to copy the data from CAN register space to same source address in which CPU is doing copying action using memory copy function.

    Assume that configuration of DMA is as follows:

    HW DMA is using frame count of 1 of 8 bytes with frame transfer instead of block transfer when HW CAN event occur.

    OR 

    I will try put the question in a different way.

    What would be the configuration of DMA such a way that to copy of 8 bytes which cannot be uninterrupted by CPU bus access.

    Best Regards,

    Arshad Ziyad

  • 0 in reply to Arshad moilingal
    TI__Guru**** 198766 points

    Hello Arshad,

    I am sorry for misunderstanding your question. I thought you copy the data from one SRAM address to another SRAM location using DMA too. 

    To answer your question, I cite Sunil's comment in another thread:

    Hercules device architecture is designed to minimize arbitration conditions like these. The CPU SRAM interconnect is designed such that an arbitration condition only exists if both the CPU and the DMA are accessing the same 64-bit address in the same cycle. In that rare case of the CPU and DMA (or other bus master) access the same 64-bit SRAM location in the same cycle, the read access will be delayed by one CPU clock cycle to allow the write access to complete first.

    Typically the available SRAM would be partitioned such that arbitration conditions like these do not occur. The DMA controller does provide several interrupt conditions that can be used to by the CPU to avoid running into the case you described: Frame Transfer Completed, Last Frame Transfer Started, Half Block Transfer Completed, and Block Transfer Completed.