• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 740 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137: eFuse questions (Class 2 and Class 3 errors)

Refikz
Prodigy 60 points

Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hello,

I have two questions related to eFuse:

1. Can you please explain in more details or point me to the document which describe what modules or peripherals are configured with eFuse?
That information in datasheet is missing and in this post:
e2e.ti.com/.../541591
I found that SRAM array and Flash memory is directly depended on correct operation of eFuse.
2. We are performing periodic CRC check of ROM, periodic RamEcc check, FlashEcc check and CCM-R4F module approx. every 16 sec, but we do not perform check for eFuse errors after power up.
In case of Class 2 or Class 3 error of the eFuse, are above checks sufficient to detect actual error on the system?


regards,

Refik

  • 0
    TI__Guru**** 199216 points

    Hello,

    I have forwarded your question to one of our experts. He will take a look and answer your question. Sorry for late reply.

  • 0
    TI__Mastermind 49120 points

    Hi Refik,

    There is an array of eFuses that are used to configure various electrical parameters that affect the Flash banks, Flash pump and the multiple SRAM instances on-chip. This array of eFuses is programmed during factory-test of the part, and is scanned on power-up as part of the device start-up sequence (not software-controlled). This process is termed the "eFuse auto-load" and there is SECDED logic implemented to correct any single-bit error and detect double-bit error during this auto-load. Any error during this auto-load process is flagged in the appropriate ESM status register/

    The efcCheck() routine generated by HALCoGen is used to ensure correct operation of this SECDED logic. This is critical in ensuring that the eFuse auto-load was completed correctly and that the SECDED logic used to correct any single-bit errors is also operating correctly.

    Periodic checks of Flash, SRAM do not replace the requirement to test the eFuse SECDED logic on power-up.

    Regards, Sunil