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CCS/LAUNCHXL-TMS57004: RTI MANAGEMENT on TMS570 with BQ76PL455EVM

Part Number: LAUNCHXL-TMS57004
Other Parts Discussed in Thread: BQ76PL455EVM, HALCOGEN

Tool/software: Code Composer Studio

Hello everyone,

I am trying to develop a BMS algorithm on TMS570 with BQ76PL455EVM. I need to add a rti on the code to the sample code that has been presented by Texas Instruments. 

extern void rtiCompare1Interrupt(void);
extern void rtiCompare2Interrupt(void);
extern void rtiCompare3Interrupt(void);

I have added code depicted above to sys_vim.h and code depicted below (rtiCompare1Interrupt, rtiCompare2Interrupt,rtiCompare3Interrupt, ) to sys_vim.c 

static const t_isrFuncPTR s_vim_init[96U] =
{
    &phantomInterrupt,
    &esmHighInterrupt,            /* Channel 0 */
    &phantomInterrupt,            /* Channel 1 */
    &rtiCompare0Interrupt,            /* Channel 2 */
    &rtiCompare1Interrupt,            /* Channel 3 */
    &rtiCompare2Interrupt,            /* Channel 4 */
    &rtiCompare3Interrupt,            /* Channel 5 */
    &phantomInterrupt,            /* Channel 6 */
    &phantomInterrupt,            /* Channel 7 */
    &phantomInterrupt,            /* Channel 8 */
.....
}

I have added below part to rt.c

*/
#pragma CODE_STATE(rtiCompare1Interrupt, 32)
#pragma INTERRUPT(rtiCompare1Interrupt, IRQ)

/* SourceId : RTI_SourceId_023 */
/* DesignId : RTI_DesignId_022 */
/* Requirements : HL_SR95 */
void rtiCompare1Interrupt(void)
{
/* USER CODE BEGIN (77) */
/* USER CODE END */

    rtiREG1->INTFLAG = 2U;
    rtiNotification(rtiNOTIFICATION_COMPARE1);

/* USER CODE BEGIN (78) */
/* USER CODE END */
}


/* USER CODE BEGIN (79) */
/* USER CODE END */

/** @fn void rtiCompare2Interrupt(void)
*   @brief RTI1 Compare 2 Interrupt Handler
*
*   RTI1 Compare 2 interrupt handler
*
*/
#pragma CODE_STATE(rtiCompare2Interrupt, 32)
#pragma INTERRUPT(rtiCompare2Interrupt, IRQ)

/* SourceId : RTI_SourceId_024 */
/* DesignId : RTI_DesignId_022 */
/* Requirements : HL_SR95 */
void rtiCompare2Interrupt(void)
{
/* USER CODE BEGIN (80) */
/* USER CODE END */

    rtiREG1->INTFLAG = 4U;
    rtiNotification(rtiNOTIFICATION_COMPARE2);

/* USER CODE BEGIN (81) */
/* USER CODE END */
}


/* USER CODE BEGIN (82) */
/* USER CODE END */

/** @fn void rtiCompare3Interrupt(void)
*   @brief RTI1 Compare 3 Interrupt Handler
*
*   RTI1 Compare 3 interrupt handler
*
*/
#pragma CODE_STATE(rtiCompare3Interrupt, 32)
#pragma INTERRUPT(rtiCompare3Interrupt, IRQ)

/* SourceId : RTI_SourceId_025 */
/* DesignId : RTI_DesignId_022 */
/* Requirements : HL_SR95 */
void rtiCompare3Interrupt(void)
{
/* USER CODE BEGIN (83) */
/* USER CODE END */

    rtiREG1->INTFLAG = 8U;
    rtiNotification(rtiNOTIFICATION_COMPARE3);

/* USER CODE BEGIN (84) */
/* USER CODE END */
}


and added below part to notification.c

#pragma WEAK(rtiNotification)
void rtiNotification(uint32 notification)
{

    if ( notification == rtiNOTIFICATION_COMPARE0)
    {

             printf("SELAM \r\n");

    }

    else if ( notification == rtiNOTIFICATION_COMPARE1)
    {
        RTI_TIMEOUT = 1;
    }
    else if ( notification == rtiNOTIFICATION_COMPARE2)
    {
           printf("HOP \r\n");
    }
    else if ( notification == rtiNOTIFICATION_COMPARE3)
    {
        printf("HOP \r\n");
    }
/*  enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (9) */
	/** - Clear all pending interrupts */
	//rtiREG1->INTFLAG = 0x0007000FU;

	//RTI_TIMEOUT = 1;
/* USER CODE END */

}

My interrupts are now working but now I can not read voltage value etc from BQ76PL455EVM. All readings are 0. When I revert code to the previous version. It works again but on that condition I do not have any timer interrupt.

Min Cell : 1 , Voltage : 0.000000
Max Cell : 0 , Voltage : 0.000000
Pack Voltage= 0.000000

What may be wrong. How can I solve that problem?

Thanks.

  • Hello Yusuf,

    If the CPU handles your 3 RTI interrupts all the time, it doesn't have time to execute other code to read the data from BQ76.

  • Actually I thought that and decreased timers to 2 and increased timer period but that did not change end of the story. Still does not work . 

    Do you have any idea?

  • Hello Turkey,

    Are you able to read the data back from BQ76 device if the all the RTI interrupts are disabled?

  • Hello Wang,

    Unfortunately I could not do it ? There are two codes in my hand. 

    1. Code: Sample usage code for BQ76PL455EVM -> This code has only Compare0 timer. I could not understand duty of COmpare0. Does it interrupt with some time period and TMS570 checks whether there is incoming BYTE ; or Does it interrupts when communication gets data ?

    2. Code: Code that I have generated from HalCoGen that has 4 timers. It works well. But on that condition TMS570 does not get values from BQ76PL455EVM. SO I need to configure timers and interrupts but could not.

    I think my error is on s_vim_init[] function. Let me share same functions for 1.Code and 2.Code.

    1.CODE:

    ** @file sys_vim.c 
    *   @brief VIM Driver Inmplmentation File
    *   @date 25.July.2013
    *   @version 03.06.00
    *
    */
    
    /* (c) Texas Instruments 2009-2013, All rights reserved. */
    
    
    #include "sys_vim.h"
    #include "system.h"
    #include "esm.h"
    
    /* USER CODE BEGIN (0) */
    /* USER CODE END */
    
    /* Vim Ram Definition */
    /** @struct vimRam
    *   @brief Vim Ram Definition
    *
    *   This type is used to access the Vim Ram.
    */
    /** @typedef vimRAM_t
    *   @brief Vim Ram Type Definition
    *
    *   This type is used to access the Vim Ram.
    */
    typedef volatile struct vimRam
    {
        t_isrFuncPTR ISR[VIM_CHANNELS + 1U];
    } vimRAM_t;
    
    #define vimRAM ((vimRAM_t *)0xFFF82000U)
    
    static const t_isrFuncPTR s_vim_init[129U] =
    {
        &phantomInterrupt,
        &esmHighInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &rtiCompare0Interrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &linHighLevelInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
        &phantomInterrupt,
    };
    void vimParityErrorHandler(void);
    
    /** @fn void vimInit(void)
    *   @brief Initializes VIM module
    *
    *   This function initializes VIM RAM and registers
    */
    
    void vimInit(void)
    {
    /* Initialize VIM table */
        {
            uint32 i;
    
            for (i = 0U; i < (VIM_CHANNELS + 1U); i++)
            {
                vimRAM->ISR[i] = s_vim_init[i];
            }
        }
    
        /* Set Fall-Back Address Parity Error Register */
        /*SAFETYMCUSW 439 S MR:11.3 <APPROVED> " Need to store the address of a function in a 32 bit register" */
        VIM_FBPARERR = (uint32)&vimParityErrorHandler;
    
        /* set IRQ/FIQ priorities */
        vimREG->FIRQPR0 =  SYS_FIQ
                        | (SYS_FIQ <<  1U)
                        | (SYS_IRQ <<  2U)
                        | (SYS_IRQ <<  3U)
                        | (SYS_IRQ <<  4U)
                        | (SYS_IRQ <<  5U)
                        | (SYS_IRQ <<  6U)
                        | (SYS_IRQ <<  7U)
                        | (SYS_IRQ <<  8U)
                        | (SYS_IRQ <<  9U)
                        | (SYS_IRQ << 10U)
                        | (SYS_IRQ << 11U)
                        | (SYS_IRQ << 12U)
                        | (SYS_IRQ << 13U)
                        | (SYS_IRQ << 14U)
                        | (SYS_IRQ << 15U)
                        | (SYS_IRQ << 16U)
                        | (SYS_IRQ << 17U)
                        | (SYS_IRQ << 18U)
                        | (SYS_IRQ << 19U)
                        | (SYS_IRQ << 20U)
                        | (SYS_IRQ << 21U)
                        | (SYS_IRQ << 22U)
                        | (SYS_IRQ << 23U)
                        | (SYS_IRQ << 24U)
                        | (SYS_IRQ << 25U)
                        | (SYS_IRQ << 26U)
                        | (SYS_IRQ << 27U)
                        | (SYS_IRQ << 28U)
                        | (SYS_IRQ << 29U)
                        | (SYS_IRQ << 30U)
                        | (SYS_IRQ << 31U);
    
        vimREG->FIRQPR1 =  SYS_IRQ
                        | (SYS_IRQ <<  1U)
                        | (SYS_IRQ <<  2U)
                        | (SYS_IRQ <<  3U)
                        | (SYS_IRQ <<  4U)
                        | (SYS_IRQ <<  5U)
                        | (SYS_IRQ <<  6U)
                        | (SYS_IRQ <<  7U)
                        | (SYS_IRQ <<  8U)
                        | (SYS_IRQ <<  9U)
                        | (SYS_IRQ << 10U)
                        | (SYS_IRQ << 11U)
                        | (SYS_IRQ << 12U)
                        | (SYS_IRQ << 13U)
                        | (SYS_IRQ << 14U)
                        | (SYS_IRQ << 15U)
                        | (SYS_IRQ << 16U)
                        | (SYS_IRQ << 17U)
                        | (SYS_IRQ << 18U)
                        | (SYS_IRQ << 19U)
                        | (SYS_IRQ << 20U)
                        | (SYS_IRQ << 21U)
                        | (SYS_IRQ << 22U)
                        | (SYS_IRQ << 23U)
                        | (SYS_IRQ << 24U)
                        | (SYS_IRQ << 25U)
                        | (SYS_IRQ << 26U)
                        | (SYS_IRQ << 27U)
                        | (SYS_IRQ << 28U)
                        | (SYS_IRQ << 29U)
                        | (SYS_IRQ << 30U)
                        | (SYS_IRQ << 31U);
    
    
        vimREG->FIRQPR2 =  SYS_IRQ
                        | (SYS_IRQ << 1U)
                        | (SYS_IRQ << 2U)
                        | (SYS_IRQ << 3U)
                        | (SYS_IRQ << 4U)
                        | (SYS_IRQ << 5U)
                        | (SYS_IRQ << 6U)
                        | (SYS_IRQ << 7U)
                        | (SYS_IRQ << 8U)
                        | (SYS_IRQ << 9U)
                        | (SYS_IRQ << 10U)
                        | (SYS_IRQ << 11U)
                        | (SYS_IRQ << 12U)
                        | (SYS_IRQ << 13U)
                        | (SYS_IRQ << 14U)
                        | (SYS_IRQ << 15U)
                        | (SYS_IRQ << 16U)
                        | (SYS_IRQ << 17U)
                        | (SYS_IRQ << 18U)
                        | (SYS_IRQ << 19U)
                        | (SYS_IRQ << 20U)
                        | (SYS_IRQ << 21U)
                        | (SYS_IRQ << 22U)
                        | (SYS_IRQ << 23U)
                        | (SYS_IRQ << 24U)
                        | (SYS_IRQ << 25U)
                        | (SYS_IRQ << 26U)
                        | (SYS_IRQ << 27U)
                        | (SYS_IRQ << 28U)
                        | (SYS_IRQ << 29U)
                        | (SYS_IRQ << 30U)
                        | (SYS_IRQ << 31U);
    
        vimREG->FIRQPR3 =  SYS_IRQ
                        | (SYS_IRQ << 1U)
                        | (SYS_IRQ << 2U)
                        | (SYS_IRQ << 3U)
                        | (SYS_IRQ << 4U)
                        | (SYS_IRQ << 5U)
                        | (SYS_IRQ << 6U)
                        | (SYS_IRQ << 7U)
                        | (SYS_IRQ << 8U)
                        | (SYS_IRQ << 9U)
                        | (SYS_IRQ << 10U)
                        | (SYS_IRQ << 11U)
                        | (SYS_IRQ << 12U)
                        | (SYS_IRQ << 13U)
                        | (SYS_IRQ << 14U)
                        | (SYS_IRQ << 15U)
                        | (SYS_IRQ << 16U)
                        | (SYS_IRQ << 17U)
                        | (SYS_IRQ << 18U)
                        | (SYS_IRQ << 19U)
                        | (SYS_IRQ << 20U)
                        | (SYS_IRQ << 21U)
                        | (SYS_IRQ << 22U)
                        | (SYS_IRQ << 23U)
                        | (SYS_IRQ << 24U)
                        | (SYS_IRQ << 25U)
                        | (SYS_IRQ << 26U)
                        | (SYS_IRQ << 27U)
                        | (SYS_IRQ << 28U)
                        | (SYS_IRQ << 29U)
                        | (SYS_IRQ << 30U)
                        | (SYS_IRQ << 31U);
    
    
        /* enable interrupts */
        vimREG->REQMASKSET0 = 1U
                            | (1U << 1U)
                            | (0U << 2U)
                            | (1U << 3U)
                            | (0U << 4U)
                            | (0U << 5U)
                            | (0U << 6U)
                            | (0U << 7U)
                            | (0U << 8U)
                            | (0U << 9U)
                            | (0U << 10U)
                            | (0U << 11U)
                            | (0U << 12U)
                            | (1U << 13U)
                            | (0U << 14U)
                            | (0U << 15U)
                            | (0U << 16U)
                            | (0U << 17U)
                            | (0U << 18U)
                            | (0U << 19U)
                            | (0U << 20U)
                            | (0U << 21U)
                            | (0U << 22U)
                            | (0U << 23U)
                            | (0U << 24U)
                            | (0U << 25U)
                            | (0U << 26U)
                            | (0U << 27U)
                            | (0U << 28U)
                            | (0U << 29U)
                            | (0U << 30U)
                            | (0U << 31U);
    
        vimREG->REQMASKSET1 = 0U
                            | (0U << 1U)
                            | (0U << 2U)
                            | (0U << 3U)
                            | (0U << 4U)
                            | (0U << 5U)
                            | (0U << 6U)
                            | (0U << 7U)
                            | (0U << 8U)
                            | (0U << 9U)
                            | (0U << 10U)
                            | (0U << 11U)
                            | (0U << 12U)
                            | (0U << 13U)
                            | (0U << 14U)
                            | (0U << 15U)
                            | (0U << 16U)
                            | (0U << 17U)
                            | (0U << 18U)
                            | (0U << 19U)
                            | (0U << 20U)
                            | (0U << 21U)
                            | (0U << 22U)
                            | (0U << 23U)
                            | (0U << 24U)
                            | (0U << 25U)
                            | (0U << 26U)
                            | (0U << 27U)
                            | (0U << 28U)
                            | (0U << 29U)
                            | (0U << 30U)
                            | (0U << 31U);
    
        vimREG->REQMASKSET2 = 0U
                            | (0U << 1U)
                            | (0U << 2U)
                            | (0U << 3U)
                            | (0U << 4U)
                            | (0U << 5U)
                            | (0U << 6U)
                            | (0U << 7U)
                            | (0U << 8U)
                            | (0U << 9U)
                            | (0U << 10U)
                            | (0U << 11U)
                            | (0U << 12U)
                            | (0U << 13U)
                            | (0U << 14U)
                            | (0U << 15U)
                            | (0U << 16U)
                            | (0U << 17U)
                            | (0U << 18U)
                            | (0U << 19U)
                            | (0U << 20U)
                            | (0U << 21U)
                            | (0U << 22U)
                            | (0U << 23U)
                            | (0U << 24U)
                            | (0U << 25U)
                            | (0U << 26U)
                            | (0U << 27U)
                            | (0U << 28U)
                            | (0U << 29U)
                            | (0U << 30U)
                            | (0U << 31U);
    
        vimREG->REQMASKSET3 =  0U
                            | (0U << 1U)
                            | (0U << 2U)
                            | (0U << 3U)
                            | (0U << 4U)
                            | (0U << 5U)
                            | (0U << 6U)
                            | (0U << 7U)
                            | (0U << 8U)
                            | (0U << 9U)
                            | (0U << 10U)
                            | (0U << 11U)
                            | (0U << 12U)
                            | (0U << 13U)
                            | (0U << 14U)
                            | (0U << 15U)
                            | (0U << 16U)
                            | (0U << 17U)
                            | (0U << 18U)
                            | (0U << 19U)
                            | (0U << 20U)
                            | (0U << 21U)
                            | (0U << 22U)
                            | (0U << 23U)
                            | (0U << 24U)
                            | (0U << 25U)
                            | (0U << 26U)
                            | (0U << 27U)
                            | (0U << 28U)
                            | (0U << 29U)
                            | (0U << 30U)
                            | (0U << 31U);
    }
    
    /** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
    *   @brief Map selected interrupt request to the selected channel
    *
    *    @param[in] request: Interrupt request number 2..95
    *    @param[in] channel: VIM Channel number 2..95
    *    @param[in] handler: Address of the interrupt handler
    *
    *   This function will map selected interrupt request to the selected channel.
    *
    */
    void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
    {
        uint32 i,j;
        i = channel >> 2U;              /* Find the register to configure */
        j = channel -(i<<2U);           /* Find the offset of the type    */
        j = 3U-j;                       /* reverse the byte order         */
        j = j<<3U;                      /* find the bit location          */
    
        /*Mapping the required interrupt request to the required channel*/
        vimREG->CHANCTRL[i] &= ~(0xFFU << j);
        vimREG->CHANCTRL[i] |= (request << j);
    
        /*Updating VIMRAM*/
        vimRAM->ISR[channel+1] = handler;
    }
    
    /** @fn void vimEnableInterrupt(uint32 channel, boolean inttype)
    *   @brief Enable interrupt for the the selected channel
    *
    *    @param[in] channel: VIM Channel number 2..95
    *    @param[in] handler: Interrupt type
    *                        - SYS_IRQ: Selected channel will be enabled as IRQ
    *                        - SYS_FIQ: Selected channel will be enabled as FIQ
    *
    *   This function will enable interrupt for the selected channel.
    *
    */
    void vimEnableInterrupt(uint32 channel, boolean inttype)
    {
        if (channel >= 64U)
        {
            if(inttype == SYS_IRQ)
            {
                vimREG->FIRQPR2 &= ~(1U << (channel-64U));
            }
            else
            {
                vimREG->FIRQPR2 |= 1U << (channel-64U);
            }
            vimREG->REQMASKSET2 = 1U << (channel-64U);
        }
        else if (channel >= 32U)
        {
            if(inttype == SYS_IRQ)
            {
                vimREG->FIRQPR1 &= ~(1U << (channel-32U));
            }
            else
            {
                vimREG->FIRQPR1 |= 1U << (channel-32U);
            }
            vimREG->REQMASKSET1 = 1U << (channel-32U);
        }
        else if (channel >= 2U)
        {
            if(inttype == SYS_IRQ)
            {
                vimREG->FIRQPR0 &= ~(1U << channel);
            }
            else
            {
                vimREG->FIRQPR0 |= 1U << channel;
            }
            vimREG->REQMASKSET0 = 1U << channel;
        }
        else
        {
            /* Empty */
        }
    }
    
    /** @fn void vimDisableInterrupt(uint32 channel)
    *   @brief Disable interrupt for the the selected channel
    *
    *    @param[in] channel: VIM Channel number 2..95
    *
    *   This function will disable interrupt for the selected channel.
    *
    */
    void vimDisableInterrupt(uint32 channel)
    {
        if (channel >= 64U)
        {
            vimREG->REQMASKCLR2 = 1U << (channel-64U);
        }
        else if (channel >=32U)
        {
            vimREG->REQMASKCLR1 = 1U << (channel-32U);
        }
        else if (channel >= 2U)
        {
            vimREG->REQMASKCLR0 = 1U << channel;
        }
        else
        {
            /* Empty */
        }
    }
    
    /* USER CODE BEGIN (1) */
    /* USER CODE END */
    
    /** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
    *   @brief Get the initial or current values of the configuration registers
    *
    *    @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
    *    @param[in] type:     whether initial or current value of the configuration registers need to be stored
    *                        - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
    *                        - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
    *
    *   This function will copy the initial or current value (depending on the parameter 'type') of the configuration 
    *   registers to the struct pointed by config_reg
    *
    */
    
    void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
    {  
        if (type == InitialValue)
        {
            config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE;
            config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE;
            config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE;
            config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE;
            config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE;
            config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE;
            config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE;
            config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE;
            config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE;
            config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE;
            config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE;
            config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE;
            config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[0] = VIM_CHANCTRL0_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[1] = VIM_CHANCTRL1_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[2] = VIM_CHANCTRL2_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[3] = VIM_CHANCTRL3_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[4] = VIM_CHANCTRL4_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[5] = VIM_CHANCTRL5_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[6] = VIM_CHANCTRL6_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[7] = VIM_CHANCTRL7_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[8] = VIM_CHANCTRL8_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[9] = VIM_CHANCTRL9_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[10] = VIM_CHANCTRL10_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[11] = VIM_CHANCTRL11_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[12] = VIM_CHANCTRL12_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[13] = VIM_CHANCTRL13_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[14] = VIM_CHANCTRL14_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[15] = VIM_CHANCTRL15_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[16] = VIM_CHANCTRL16_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[17] = VIM_CHANCTRL17_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[18] = VIM_CHANCTRL18_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[19] = VIM_CHANCTRL19_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[20] = VIM_CHANCTRL20_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[21] = VIM_CHANCTRL21_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[22] = VIM_CHANCTRL22_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[23] = VIM_CHANCTRL23_CONFIGVALUE;
        }
        else
        {
        /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Register read back support" */
            config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0;
            config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1;
            config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2;
            config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3;
            config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0;
            config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1;
            config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2;
            config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3;
            config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0;
            config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1;
            config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2;
            config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3;
            config_reg->CONFIG_CAPEVT = vimREG->CAPEVT;
            config_reg->CONFIG_CHANCTRL[0] = vimREG->CHANCTRL[0];
            config_reg->CONFIG_CHANCTRL[1] = vimREG->CHANCTRL[1];
            config_reg->CONFIG_CHANCTRL[2] = vimREG->CHANCTRL[2];
            config_reg->CONFIG_CHANCTRL[3] = vimREG->CHANCTRL[3];
            config_reg->CONFIG_CHANCTRL[4] = vimREG->CHANCTRL[4];
            config_reg->CONFIG_CHANCTRL[5] = vimREG->CHANCTRL[5];
            config_reg->CONFIG_CHANCTRL[6] = vimREG->CHANCTRL[6];
            config_reg->CONFIG_CHANCTRL[7] = vimREG->CHANCTRL[7];
            config_reg->CONFIG_CHANCTRL[8] = vimREG->CHANCTRL[8];
            config_reg->CONFIG_CHANCTRL[9] = vimREG->CHANCTRL[9];
            config_reg->CONFIG_CHANCTRL[10] = vimREG->CHANCTRL[10];
            config_reg->CONFIG_CHANCTRL[11] = vimREG->CHANCTRL[11];
            config_reg->CONFIG_CHANCTRL[12] = vimREG->CHANCTRL[12];
            config_reg->CONFIG_CHANCTRL[13] = vimREG->CHANCTRL[13];
            config_reg->CONFIG_CHANCTRL[14] = vimREG->CHANCTRL[14];
            config_reg->CONFIG_CHANCTRL[15] = vimREG->CHANCTRL[15];
            config_reg->CONFIG_CHANCTRL[16] = vimREG->CHANCTRL[16];
            config_reg->CONFIG_CHANCTRL[17] = vimREG->CHANCTRL[17];
            config_reg->CONFIG_CHANCTRL[18] = vimREG->CHANCTRL[18];
            config_reg->CONFIG_CHANCTRL[19] = vimREG->CHANCTRL[19];
            config_reg->CONFIG_CHANCTRL[20] = vimREG->CHANCTRL[20];
            config_reg->CONFIG_CHANCTRL[21] = vimREG->CHANCTRL[21];
            config_reg->CONFIG_CHANCTRL[22] = vimREG->CHANCTRL[22];
            config_reg->CONFIG_CHANCTRL[23] = vimREG->CHANCTRL[23];
    
    
    
        }
    }
    
    
    #pragma CODE_STATE(vimParityErrorHandler, 32)
    #pragma INTERRUPT(vimParityErrorHandler, IRQ)
    #pragma WEAK(vimParityErrorHandler)
    
    void vimParityErrorHandler(void)
    {
        uint32 vec;
    
        /* Identify the corrupted address */
        uint32 error_addr = VIM_ADDERR;
    
        /* Identify the channel number */
        uint32 error_channel = ((error_addr & 0x1FFU) >> 2U) - 1U;
    
        /* Correct the corrupted location */
        vimRAM->ISR[error_channel + 1U] = s_vim_init[error_channel + 1U];
    
        /* Clear Parity Error Flag */
        VIM_PARFLG = 1U;
    
        /* Disable and enable the highest priority pending channel */
        if (vimREG->FIQINDEX != 0U)
        {
            vec = vimREG->FIQINDEX - 1U;
        }
        else
        {
           /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Read 32 bit volatile register" */
            vec = vimREG->IRQINDEX - 1U;
        }
        if(vec == 0U)
        {
            vimREG->INTREQ0 = 1U;
            vec = esmREG->IOFFHR - 1U;
    
            if (vec < 32U)
            {
                esmREG->SR1[0U] = 1U << vec;
                esmGroup1Notification(vec);
            }
            else if (vec < 64U)
            {
                esmREG->SR1[1U] = 1U << (vec-32U);
                esmGroup2Notification(vec-32U);
            }
            else if (vec < 96U)
            {
                esmREG->SR4[0U] = 1U << (vec-64U);
                esmGroup1Notification(vec-32U);
            }
            else if (vec < 128U)
            {
                esmREG->SR4[1U] = 1U << (vec-96U);
                esmGroup2Notification(vec-64U);
            }
        }
        else if (vec < 32U)
        {
            vimREG->REQMASKCLR0 = 1U << vec;
            vimREG->REQMASKSET0 = 1U << vec;
        }
        else if (vec < 64U)
        {
            vimREG->REQMASKCLR1 = 1U << (vec-32U);
            vimREG->REQMASKSET1 = 1U << (vec-32U);
        }
        else
        {
            vimREG->REQMASKCLR2 = 1U << (vec-64U);
            vimREG->REQMASKSET2 = 1U << (vec-64U);
        }
    
    }

    2.CODE

    /** @file sys_vim.c 
    *   @brief VIM Driver Implementation File
    *   @date 11-Dec-2018
    *   @version 04.07.01
    *
    */
    
    /*
    * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
    *
    *
    *  Redistribution and use in source and binary forms, with or without
    *  modification, are permitted provided that the following conditions
    *  are met:
    *
    *    Redistributions of source code must retain the above copyright
    *    notice, this list of conditions and the following disclaimer.
    *
    *    Redistributions in binary form must reproduce the above copyright
    *    notice, this list of conditions and the following disclaimer in the
    *    documentation and/or other materials provided with the
    *    distribution.
    *
    *    Neither the name of Texas Instruments Incorporated nor the names of
    *    its contributors may be used to endorse or promote products derived
    *    from this software without specific prior written permission.
    *
    *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    */
    
    
    
    #include "sys_vim.h"
    #include "system.h"
    #include "esm.h"
    
    /* USER CODE BEGIN (0) */
    /* USER CODE END */
    
    /* Vim Ram Definition */
    /** @struct vimRam
    *   @brief Vim Ram Definition
    *
    *   This type is used to access the Vim Ram.
    */
    /** @typedef vimRAM_t
    *   @brief Vim Ram Type Definition
    *
    *   This type is used to access the Vim Ram.
    */
    typedef volatile struct vimRam
    {
        t_isrFuncPTR ISR[VIM_CHANNELS];
    } vimRAM_t;
    
    #define vimRAM ((vimRAM_t *)0xFFF82000U)
    
    static const t_isrFuncPTR s_vim_init[96U] =
    {
        &phantomInterrupt,
        &esmHighInterrupt,            /* Channel 0 */
        &phantomInterrupt,            /* Channel 1 */
        &rtiCompare0Interrupt,            /* Channel 2 */
        &rtiCompare1Interrupt,            /* Channel 3 */
        &rtiCompare2Interrupt,            /* Channel 4 */
        &rtiCompare3Interrupt,            /* Channel 5 */
        &phantomInterrupt,            /* Channel 6 */
        &phantomInterrupt,            /* Channel 7 */
        &phantomInterrupt,            /* Channel 8 */
        &phantomInterrupt,            /* Channel 9 */
        &phantomInterrupt,            /* Channel 10 */
        &phantomInterrupt,            /* Channel 11 */
        &phantomInterrupt,            /* Channel 12 */
        &phantomInterrupt,            /* Channel 13 */
        &phantomInterrupt,            /* Channel 14 */
        &phantomInterrupt,            /* Channel 15 */
        &phantomInterrupt,            /* Channel 16 */
        &phantomInterrupt,            /* Channel 17 */
        &phantomInterrupt,            /* Channel 18 */
        &phantomInterrupt,            /* Channel 19 */
        &phantomInterrupt,            /* Channel 20 */
        &phantomInterrupt,            /* Channel 21 */
        &phantomInterrupt,            /* Channel 22 */
        &phantomInterrupt,            /* Channel 23 */
        &phantomInterrupt,            /* Channel 24 */
        &phantomInterrupt,            /* Channel 25 */
        &phantomInterrupt,            /* Channel 26 */
        &phantomInterrupt,            /* Channel 27 */
        &phantomInterrupt,            /* Channel 28 */
        &phantomInterrupt,            /* Channel 29 */
        &phantomInterrupt,            /* Channel 30 */
        &phantomInterrupt,            /* Channel 31 */
        &phantomInterrupt,            /* Channel 32 */
        &phantomInterrupt,            /* Channel 33 */
        &phantomInterrupt,            /* Channel 34 */
        &phantomInterrupt,            /* Channel 35 */
        &phantomInterrupt,            /* Channel 36 */
        &phantomInterrupt,            /* Channel 37 */
        &phantomInterrupt,            /* Channel 38 */
        &phantomInterrupt,            /* Channel 39 */
        &phantomInterrupt,            /* Channel 40 */
        &phantomInterrupt,            /* Channel 41 */
        &phantomInterrupt,            /* Channel 42 */
        &phantomInterrupt,            /* Channel 43 */
        &phantomInterrupt,            /* Channel 44 */
        &phantomInterrupt,            /* Channel 45 */
        &phantomInterrupt,            /* Channel 46 */
        &phantomInterrupt,            /* Channel 47 */
        &phantomInterrupt,            /* Channel 48 */
        &phantomInterrupt,            /* Channel 49 */
        &phantomInterrupt,            /* Channel 50 */
        &phantomInterrupt,            /* Channel 51 */
        &phantomInterrupt,            /* Channel 52 */
        &phantomInterrupt,            /* Channel 53 */
        &phantomInterrupt,            /* Channel 54 */
        &phantomInterrupt,            /* Channel 55 */
        &phantomInterrupt,            /* Channel 56 */
        &phantomInterrupt,            /* Channel 57 */
        &phantomInterrupt,            /* Channel 58 */
        &phantomInterrupt,            /* Channel 59 */
        &phantomInterrupt,            /* Channel 60 */
        &phantomInterrupt,            /* Channel 61 */
        &phantomInterrupt,            /* Channel 62 */
        &phantomInterrupt,            /* Channel 63 */
        &phantomInterrupt,            /* Channel 64 */
        &phantomInterrupt,            /* Channel 65 */
        &phantomInterrupt,            /* Channel 66 */
        &phantomInterrupt,            /* Channel 67 */
        &phantomInterrupt,            /* Channel 68 */
        &phantomInterrupt,            /* Channel 69 */
        &phantomInterrupt,            /* Channel 70 */
        &phantomInterrupt,            /* Channel 71 */
        &phantomInterrupt,            /* Channel 72 */
        &phantomInterrupt,            /* Channel 73 */
        &phantomInterrupt,            /* Channel 74 */
        &phantomInterrupt,            /* Channel 75 */
        &phantomInterrupt,            /* Channel 76 */
        &phantomInterrupt,            /* Channel 77 */
        &phantomInterrupt,            /* Channel 78 */
        &phantomInterrupt,            /* Channel 79 */
        &phantomInterrupt,            /* Channel 80 */
        &phantomInterrupt,            /* Channel 81 */
        &phantomInterrupt,            /* Channel 82 */
        &phantomInterrupt,            /* Channel 83 */
        &phantomInterrupt,            /* Channel 84 */
        &phantomInterrupt,            /* Channel 85 */
        &phantomInterrupt,            /* Channel 86 */
        &phantomInterrupt,            /* Channel 87 */
        &phantomInterrupt,            /* Channel 88 */
        &phantomInterrupt,            /* Channel 89 */
        &phantomInterrupt,            /* Channel 90 */
        &phantomInterrupt,            /* Channel 91 */
        &phantomInterrupt,            /* Channel 92 */
        &phantomInterrupt,            /* Channel 93 */
        &phantomInterrupt,            /* Channel 94 */
    };
    
    void vimParityErrorHandler(void);
    
    /** @fn void vimInit(void)
    *   @brief Initializes VIM module
    *
    *   This function initializes VIM RAM and registers
    */
    /* SourceId : VIM_SourceId_001 */
    /* DesignId : VIM_DesignId_001 */
    /* Requirements : HL_SR100 */
    void vimInit(void)
    {
        /* VIM RAM Parity Enable */
        VIM_PARCTL = 0xAU;
    
        /* Initialize VIM table */
        {
            uint32 i;
    
            for (i = 0U; i < VIM_CHANNELS; i++)
            {
                vimRAM->ISR[i] = s_vim_init[i];
            }
        }
        
        /* Set Fall-Back Address Parity Error Register */
        /*SAFETYMCUSW 439 S MR:11.3 <APPROVED> " Need to store the address of a function in a 32 bit register - Advisory as per MISRA" */
        VIM_FBPARERR = (uint32)&vimParityErrorHandler;
    
        /* set IRQ/FIQ priorities */
        vimREG->FIRQPR0 = (uint32)((uint32)SYS_FIQ << 0U)
                        | (uint32)((uint32)SYS_FIQ << 1U)
                        | (uint32)((uint32)SYS_IRQ << 2U)
                        | (uint32)((uint32)SYS_IRQ << 3U)
                        | (uint32)((uint32)SYS_IRQ << 4U)
                        | (uint32)((uint32)SYS_IRQ << 5U)
                        | (uint32)((uint32)SYS_IRQ << 6U)
                        | (uint32)((uint32)SYS_IRQ << 7U)
                        | (uint32)((uint32)SYS_IRQ << 8U)
                        | (uint32)((uint32)SYS_IRQ << 9U)
                        | (uint32)((uint32)SYS_IRQ << 10U)
                        | (uint32)((uint32)SYS_IRQ << 11U)
                        | (uint32)((uint32)SYS_IRQ << 12U)
                        | (uint32)((uint32)SYS_IRQ << 13U)
                        | (uint32)((uint32)SYS_IRQ << 14U)
                        | (uint32)((uint32)SYS_IRQ << 15U)
                        | (uint32)((uint32)SYS_IRQ << 16U)
                        | (uint32)((uint32)SYS_IRQ << 17U)
                        | (uint32)((uint32)SYS_IRQ << 18U)
                        | (uint32)((uint32)SYS_IRQ << 19U)
                        | (uint32)((uint32)SYS_IRQ << 20U)
                        | (uint32)((uint32)SYS_IRQ << 21U)
                        | (uint32)((uint32)SYS_IRQ << 22U)
                        | (uint32)((uint32)SYS_IRQ << 23U)
                        | (uint32)((uint32)SYS_IRQ << 24U)
                        | (uint32)((uint32)SYS_IRQ << 25U)
                        | (uint32)((uint32)SYS_IRQ << 26U)
                        | (uint32)((uint32)SYS_IRQ << 27U)
                        | (uint32)((uint32)SYS_IRQ << 28U)
                        | (uint32)((uint32)SYS_IRQ << 29U)
                        | (uint32)((uint32)SYS_IRQ << 30U)
                        | (uint32)((uint32)SYS_IRQ << 31U);
    
        vimREG->FIRQPR1 = (uint32)((uint32)SYS_IRQ << 0U)
                        | (uint32)((uint32)SYS_IRQ << 1U)
                        | (uint32)((uint32)SYS_IRQ << 2U)
                        | (uint32)((uint32)SYS_IRQ << 3U)
                        | (uint32)((uint32)SYS_IRQ << 4U)
                        | (uint32)((uint32)SYS_IRQ << 5U)
                        | (uint32)((uint32)SYS_IRQ << 6U)
                        | (uint32)((uint32)SYS_IRQ << 7U)
                        | (uint32)((uint32)SYS_IRQ << 8U)
                        | (uint32)((uint32)SYS_IRQ << 9U)
                        | (uint32)((uint32)SYS_IRQ << 10U)
                        | (uint32)((uint32)SYS_IRQ << 11U)
                        | (uint32)((uint32)SYS_IRQ << 12U)
                        | (uint32)((uint32)SYS_IRQ << 13U)
                        | (uint32)((uint32)SYS_IRQ << 14U)
                        | (uint32)((uint32)SYS_IRQ << 15U)
                        | (uint32)((uint32)SYS_IRQ << 16U)
                        | (uint32)((uint32)SYS_IRQ << 17U)
                        | (uint32)((uint32)SYS_IRQ << 18U)
                        | (uint32)((uint32)SYS_IRQ << 19U)
                        | (uint32)((uint32)SYS_IRQ << 20U)
                        | (uint32)((uint32)SYS_IRQ << 21U)
                        | (uint32)((uint32)SYS_IRQ << 22U)
                        | (uint32)((uint32)SYS_IRQ << 23U)
                        | (uint32)((uint32)SYS_IRQ << 24U)
                        | (uint32)((uint32)SYS_IRQ << 25U)
                        | (uint32)((uint32)SYS_IRQ << 26U)
                        | (uint32)((uint32)SYS_IRQ << 27U)
                        | (uint32)((uint32)SYS_IRQ << 28U)
                        | (uint32)((uint32)SYS_IRQ << 29U)
                        | (uint32)((uint32)SYS_IRQ << 30U)
                        | (uint32)((uint32)SYS_IRQ << 31U);
    
    
        vimREG->FIRQPR2 = (uint32)((uint32)SYS_IRQ << 0U)
                        | (uint32)((uint32)SYS_IRQ << 1U)
                        | (uint32)((uint32)SYS_IRQ << 2U)
                        | (uint32)((uint32)SYS_IRQ << 3U)
                        | (uint32)((uint32)SYS_IRQ << 4U)
                        | (uint32)((uint32)SYS_IRQ << 5U)
                        | (uint32)((uint32)SYS_IRQ << 6U)
                        | (uint32)((uint32)SYS_IRQ << 7U)
                        | (uint32)((uint32)SYS_IRQ << 8U)
                        | (uint32)((uint32)SYS_IRQ << 9U)
                        | (uint32)((uint32)SYS_IRQ << 10U)
                        | (uint32)((uint32)SYS_IRQ << 11U)
                        | (uint32)((uint32)SYS_IRQ << 12U)
                        | (uint32)((uint32)SYS_IRQ << 13U)
                        | (uint32)((uint32)SYS_IRQ << 14U)
                        | (uint32)((uint32)SYS_IRQ << 15U)
                        | (uint32)((uint32)SYS_IRQ << 16U)
                        | (uint32)((uint32)SYS_IRQ << 17U)
                        | (uint32)((uint32)SYS_IRQ << 18U)
                        | (uint32)((uint32)SYS_IRQ << 19U)
                        | (uint32)((uint32)SYS_IRQ << 20U)
                        | (uint32)((uint32)SYS_IRQ << 21U)
                        | (uint32)((uint32)SYS_IRQ << 22U)
                        | (uint32)((uint32)SYS_IRQ << 23U)
                        | (uint32)((uint32)SYS_IRQ << 24U)
                        | (uint32)((uint32)SYS_IRQ << 25U)
                        | (uint32)((uint32)SYS_IRQ << 26U)
                        | (uint32)((uint32)SYS_IRQ << 27U)
                        | (uint32)((uint32)SYS_IRQ << 28U)
                        | (uint32)((uint32)SYS_IRQ << 29U)
                        | (uint32)((uint32)SYS_IRQ << 30U)
                        | (uint32)((uint32)SYS_IRQ << 31U);
    
        vimREG->FIRQPR3 = (uint32)((uint32)SYS_IRQ << 0U)
                        | (uint32)((uint32)SYS_IRQ << 1U)
                        | (uint32)((uint32)SYS_IRQ << 2U)
                        | (uint32)((uint32)SYS_IRQ << 3U)
                        | (uint32)((uint32)SYS_IRQ << 4U)
                        | (uint32)((uint32)SYS_IRQ << 5U)
                        | (uint32)((uint32)SYS_IRQ << 6U)
                        | (uint32)((uint32)SYS_IRQ << 7U)
                        | (uint32)((uint32)SYS_IRQ << 8U)
                        | (uint32)((uint32)SYS_IRQ << 9U)
                        | (uint32)((uint32)SYS_IRQ << 10U)
                        | (uint32)((uint32)SYS_IRQ << 11U)
                        | (uint32)((uint32)SYS_IRQ << 12U)
                        | (uint32)((uint32)SYS_IRQ << 13U)
                        | (uint32)((uint32)SYS_IRQ << 14U)
                        | (uint32)((uint32)SYS_IRQ << 15U)
                        | (uint32)((uint32)SYS_IRQ << 16U)
                        | (uint32)((uint32)SYS_IRQ << 17U)
                        | (uint32)((uint32)SYS_IRQ << 18U)
                        | (uint32)((uint32)SYS_IRQ << 19U)
                        | (uint32)((uint32)SYS_IRQ << 20U)
                        | (uint32)((uint32)SYS_IRQ << 21U)
                        | (uint32)((uint32)SYS_IRQ << 22U)
                        | (uint32)((uint32)SYS_IRQ << 23U)
                        | (uint32)((uint32)SYS_IRQ << 24U)
                        | (uint32)((uint32)SYS_IRQ << 25U)
                        | (uint32)((uint32)SYS_IRQ << 26U)
                        | (uint32)((uint32)SYS_IRQ << 27U)
                        | (uint32)((uint32)SYS_IRQ << 28U)
                        | (uint32)((uint32)SYS_IRQ << 29U)
                        | (uint32)((uint32)SYS_IRQ << 30U)
                        | (uint32)((uint32)SYS_IRQ << 31U);
    
                        
        /* enable interrupts */
        vimREG->REQMASKSET0 = (uint32)((uint32)1U << 0U)
                            | (uint32)((uint32)1U << 1U)
                            | (uint32)((uint32)1U << 2U)
                            | (uint32)((uint32)1U << 3U)
                            | (uint32)((uint32)1U << 4U)
                            | (uint32)((uint32)1U << 5U)
                            | (uint32)((uint32)0U << 6U)
                            | (uint32)((uint32)0U << 7U)
                            | (uint32)((uint32)0U << 8U)
                            | (uint32)((uint32)0U << 9U)
                            | (uint32)((uint32)0U << 10U)
                            | (uint32)((uint32)0U << 11U)
                            | (uint32)((uint32)0U << 12U)
                            | (uint32)((uint32)0U << 13U)
                            | (uint32)((uint32)0U << 14U)
                            | (uint32)((uint32)0U << 15U)
                            | (uint32)((uint32)0U << 16U)
                            | (uint32)((uint32)0U << 17U)
                            | (uint32)((uint32)0U << 18U)
                            | (uint32)((uint32)0U << 19U)
                            | (uint32)((uint32)0U << 20U)
                            | (uint32)((uint32)0U << 21U)
                            | (uint32)((uint32)0U << 22U)
                            | (uint32)((uint32)0U << 23U)
                            | (uint32)((uint32)0U << 24U)
                            | (uint32)((uint32)0U << 25U)
                            | (uint32)((uint32)0U << 26U)
                            | (uint32)((uint32)0U << 27U)
                            | (uint32)((uint32)0U << 28U)
                            | (uint32)((uint32)0U << 29U)
                            | (uint32)((uint32)0U << 30U)
                            | (uint32)((uint32)0U << 31U);
    
        vimREG->REQMASKSET1 = (uint32)((uint32)0U << 0U)
                            | (uint32)((uint32)0U << 1U)
                            | (uint32)((uint32)0U << 2U)
                            | (uint32)((uint32)0U << 3U)
                            | (uint32)((uint32)0U << 4U)
                            | (uint32)((uint32)0U << 5U)
                            | (uint32)((uint32)0U << 6U)
                            | (uint32)((uint32)0U << 7U)
                            | (uint32)((uint32)0U << 8U)
                            | (uint32)((uint32)0U << 9U)
                            | (uint32)((uint32)0U << 10U)
                            | (uint32)((uint32)0U << 11U)
                            | (uint32)((uint32)0U << 12U)
                            | (uint32)((uint32)0U << 13U)
                            | (uint32)((uint32)0U << 14U)
                            | (uint32)((uint32)0U << 15U)
                            | (uint32)((uint32)0U << 16U)
                            | (uint32)((uint32)0U << 17U)
                            | (uint32)((uint32)0U << 18U)
                            | (uint32)((uint32)0U << 19U)
                            | (uint32)((uint32)0U << 20U)
                            | (uint32)((uint32)0U << 21U)
                            | (uint32)((uint32)0U << 22U)
                            | (uint32)((uint32)0U << 23U)
                            | (uint32)((uint32)0U << 24U)
                            | (uint32)((uint32)0U << 25U)
                            | (uint32)((uint32)0U << 26U)
                            | (uint32)((uint32)0U << 27U)
                            | (uint32)((uint32)0U << 28U)
                            | (uint32)((uint32)0U << 29U)
                            | (uint32)((uint32)0U << 30U)
                            | (uint32)((uint32)0U << 31U);
    
        vimREG->REQMASKSET2 = (uint32)((uint32)0U << 0U)
                            | (uint32)((uint32)0U << 1U)
                            | (uint32)((uint32)0U << 2U)
                            | (uint32)((uint32)0U << 3U)
                            | (uint32)((uint32)0U << 4U)
                            | (uint32)((uint32)0U << 5U)
                            | (uint32)((uint32)0U << 6U)
                            | (uint32)((uint32)0U << 7U)
                            | (uint32)((uint32)0U << 8U)
                            | (uint32)((uint32)0U << 9U)
                            | (uint32)((uint32)0U << 10U)
                            | (uint32)((uint32)0U << 11U)
                            | (uint32)((uint32)0U << 12U)
                            | (uint32)((uint32)0U << 13U)
                            | (uint32)((uint32)0U << 14U)
                            | (uint32)((uint32)0U << 15U)
                            | (uint32)((uint32)0U << 16U)
                            | (uint32)((uint32)0U << 17U)
                            | (uint32)((uint32)0U << 18U)
                            | (uint32)((uint32)0U << 19U)
                            | (uint32)((uint32)0U << 20U)
                            | (uint32)((uint32)0U << 21U)
                            | (uint32)((uint32)0U << 22U)
                            | (uint32)((uint32)0U << 23U)
                            | (uint32)((uint32)0U << 24U)
                            | (uint32)((uint32)0U << 25U)
                            | (uint32)((uint32)0U << 26U)
                            | (uint32)((uint32)0U << 27U)
                            | (uint32)((uint32)0U << 28U)
                            | (uint32)((uint32)0U << 29U)
                            | (uint32)((uint32)0U << 30U)
                            | (uint32)((uint32)0U << 31U);
                            
        vimREG->REQMASKSET3 = (uint32)((uint32)0U << 0U)
                            | (uint32)((uint32)0U << 1U)
                            | (uint32)((uint32)0U << 2U)
                            | (uint32)((uint32)0U << 3U)
                            | (uint32)((uint32)0U << 4U)
                            | (uint32)((uint32)0U << 5U)
                            | (uint32)((uint32)0U << 6U)
                            | (uint32)((uint32)0U << 7U)
                            | (uint32)((uint32)0U << 8U)
                            | (uint32)((uint32)0U << 9U)
                            | (uint32)((uint32)0U << 10U)
                            | (uint32)((uint32)0U << 11U)
                            | (uint32)((uint32)0U << 12U)
                            | (uint32)((uint32)0U << 13U)
                            | (uint32)((uint32)0U << 14U)
                            | (uint32)((uint32)0U << 15U)
                            | (uint32)((uint32)0U << 16U)
                            | (uint32)((uint32)0U << 17U)
                            | (uint32)((uint32)0U << 18U)
                            | (uint32)((uint32)0U << 19U)
                            | (uint32)((uint32)0U << 20U)
                            | (uint32)((uint32)0U << 21U)
                            | (uint32)((uint32)0U << 22U)
                            | (uint32)((uint32)0U << 23U)
                            | (uint32)((uint32)0U << 24U)
                            | (uint32)((uint32)0U << 25U)
                            | (uint32)((uint32)0U << 26U)
                            | (uint32)((uint32)0U << 27U)
                            | (uint32)((uint32)0U << 28U)
                            | (uint32)((uint32)0U << 29U)
                            | (uint32)((uint32)0U << 30U)
                            | (uint32)((uint32)0U << 31U);
    
        /* Set Capture event sources */
        vimREG->CAPEVT = ((uint32)((uint32)0U << 0U)
                         |(uint32)((uint32)0U << 16U));
    }
    
    /** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
    *   @brief Map selected interrupt request to the selected channel
    *
    *    @param[in] request: Interrupt request number 2..95
    *    @param[in] channel: VIM Channel number 2..95
    *    @param[in] handler: Address of the interrupt handler
    *
    *   This function will map selected interrupt request to the selected channel.
    *
    */
    /* SourceId : VIM_SourceId_002 */
    /* DesignId : VIM_DesignId_002 */
    /* Requirements : HL_SR101 */
    void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
    {
        uint32 i,j;
        i = channel >> 2U;              /* Find the register to configure */
        j = channel - (i << 2U);        /* Find the offset of the type    */
        j = 3U - j;                     /* reverse the byte order         */
        j = j << 3U;                    /* find the bit location          */
    
        /*Mapping the required interrupt request to the required channel*/
        vimREG->CHANCTRL[i] &= ~(uint32)((uint32)0xFFU << j);
        vimREG->CHANCTRL[i] |= (request << j);
    
        /*Updating VIMRAM*/
        vimRAM->ISR[channel + 1U] = handler;
    }
    
    /** @fn void vimEnableInterrupt(uint32 channel, boolean inttype)
    *   @brief Enable interrupt for the the selected channel
    *
    *    @param[in] channel: VIM Channel number 2..95
    *    @param[in] inttype: Interrupt type
    *                        - SYS_IRQ: Selected channel will be enabled as IRQ
    *                        - SYS_FIQ: Selected channel will be enabled as FIQ
    *
    *   This function will enable interrupt for the selected channel.
    *
    */
    /* SourceId : VIM_SourceId_003 */
    /* DesignId : VIM_DesignId_003 */
    /* Requirements : HL_SR102 */
    void vimEnableInterrupt(uint32 channel, systemInterrupt_t inttype)
    {
        if (channel >= 64U)
        {
            if(inttype == SYS_IRQ)
            {
                vimREG->FIRQPR2 &= ~(uint32)((uint32)1U << (channel-64U));
            }
            else
            {
                vimREG->FIRQPR2 |= ((uint32)1U << (channel-64U));
            }
            vimREG->REQMASKSET2 = (uint32)1U << (channel-64U);
        }
        else if (channel >= 32U)
        {
            if(inttype == SYS_IRQ)
            {
                vimREG->FIRQPR1 &= ~(uint32)((uint32)1U << (channel-32U));
            }
            else
            {
                vimREG->FIRQPR1 |= ((uint32)1U << (channel-32U));
            }
            vimREG->REQMASKSET1 = (uint32)1U << (channel-32U);
        }
        else if (channel >= 2U)
        {
            if(inttype == SYS_IRQ)
            {
                vimREG->FIRQPR0 &= ~(uint32)((uint32)1U << channel);
            }
            else
            {
                vimREG->FIRQPR0 |= ((uint32)1U << channel);
            }
            vimREG->REQMASKSET0 = (uint32)1U << channel;
        }
        else
        {
            /* Empty */
        }
    }
    
    /** @fn void vimDisableInterrupt(uint32 channel)
    *   @brief Disable interrupt for the the selected channel
    *
    *    @param[in] channel: VIM Channel number 2..95
    *
    *   This function will disable interrupt for the selected channel.
    *
    */
    /* SourceId : VIM_SourceId_004 */
    /* DesignId : VIM_DesignId_004 */
    /* Requirements : HL_SR103 */
    void vimDisableInterrupt(uint32 channel)
    {
        if (channel >= 64U)
        {
            vimREG->REQMASKCLR2 = (uint32)1U << (channel-64U);
        }
        else if (channel >=32U)
        {
            vimREG->REQMASKCLR1 = (uint32)1U << (channel-32U);
        }
        else if (channel >= 2U)
        {
            vimREG->REQMASKCLR0 = (uint32)1U << channel;
        }
        else
        {
            /* Empty */
        }
    }
    
    /* USER CODE BEGIN (1) */
    /* USER CODE END */
    
    /** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
    *   @brief Get the initial or current values of the configuration registers
    *
    *    @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
    *    @param[in] type:     whether initial or current value of the configuration registers need to be stored
    *                        - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
    *                        - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
    *
    *   This function will copy the initial or current value (depending on the parameter 'type') of the configuration 
    *   registers to the struct pointed by config_reg
    *
    */
    /* SourceId : VIM_SourceId_005 */
    /* DesignId : VIM_DesignId_005 */
    /* Requirements : HL_SR104 */
    void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
    {  
        if (type == InitialValue)
        {
            config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE;
            config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE;
            config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE;
            config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE;
            config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE;
            config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE;
            config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE;
            config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE;
            config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE;
            config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE;
            config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE;
            config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE;
            config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[0U] = VIM_CHANCTRL0_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[1U] = VIM_CHANCTRL1_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[2U] = VIM_CHANCTRL2_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[3U] = VIM_CHANCTRL3_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[4U] = VIM_CHANCTRL4_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[5U] = VIM_CHANCTRL5_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[6U] = VIM_CHANCTRL6_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[7U] = VIM_CHANCTRL7_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[8U] = VIM_CHANCTRL8_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[9U] = VIM_CHANCTRL9_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[10U] = VIM_CHANCTRL10_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[11U] = VIM_CHANCTRL11_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[12U] = VIM_CHANCTRL12_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[13U] = VIM_CHANCTRL13_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[14U] = VIM_CHANCTRL14_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[15U] = VIM_CHANCTRL15_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[16U] = VIM_CHANCTRL16_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[17U] = VIM_CHANCTRL17_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[18U] = VIM_CHANCTRL18_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[19U] = VIM_CHANCTRL19_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[20U] = VIM_CHANCTRL20_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[21U] = VIM_CHANCTRL21_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[22U] = VIM_CHANCTRL22_CONFIGVALUE;
            config_reg->CONFIG_CHANCTRL[23U] = VIM_CHANCTRL23_CONFIGVALUE;
        }
        else
        {
        /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
            config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0;
            config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1;
            config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2;
            config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3;
            config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0;
            config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1;
            config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2;
            config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3;
            config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0;
            config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1;
            config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2;
            config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3;
            config_reg->CONFIG_CAPEVT = vimREG->CAPEVT;
            config_reg->CONFIG_CHANCTRL[0U] = vimREG->CHANCTRL[0U];
            config_reg->CONFIG_CHANCTRL[1U] = vimREG->CHANCTRL[1U];
            config_reg->CONFIG_CHANCTRL[2U] = vimREG->CHANCTRL[2U];
            config_reg->CONFIG_CHANCTRL[3U] = vimREG->CHANCTRL[3U];
            config_reg->CONFIG_CHANCTRL[4U] = vimREG->CHANCTRL[4U];
            config_reg->CONFIG_CHANCTRL[5U] = vimREG->CHANCTRL[5U];
            config_reg->CONFIG_CHANCTRL[6U] = vimREG->CHANCTRL[6U];
            config_reg->CONFIG_CHANCTRL[7U] = vimREG->CHANCTRL[7U];
            config_reg->CONFIG_CHANCTRL[8U] = vimREG->CHANCTRL[8U];
            config_reg->CONFIG_CHANCTRL[9U] = vimREG->CHANCTRL[9U];
            config_reg->CONFIG_CHANCTRL[10U] = vimREG->CHANCTRL[10U];
            config_reg->CONFIG_CHANCTRL[11U] = vimREG->CHANCTRL[11U];
            config_reg->CONFIG_CHANCTRL[12U] = vimREG->CHANCTRL[12U];
            config_reg->CONFIG_CHANCTRL[13U] = vimREG->CHANCTRL[13U];
            config_reg->CONFIG_CHANCTRL[14U] = vimREG->CHANCTRL[14U];
            config_reg->CONFIG_CHANCTRL[15U] = vimREG->CHANCTRL[15U];
            config_reg->CONFIG_CHANCTRL[16U] = vimREG->CHANCTRL[16U];
            config_reg->CONFIG_CHANCTRL[17U] = vimREG->CHANCTRL[17U];
            config_reg->CONFIG_CHANCTRL[18U] = vimREG->CHANCTRL[18U];
            config_reg->CONFIG_CHANCTRL[19U] = vimREG->CHANCTRL[19U];
            config_reg->CONFIG_CHANCTRL[20U] = vimREG->CHANCTRL[20U];
            config_reg->CONFIG_CHANCTRL[21U] = vimREG->CHANCTRL[21U];
            config_reg->CONFIG_CHANCTRL[22U] = vimREG->CHANCTRL[22U];
            config_reg->CONFIG_CHANCTRL[23U] = vimREG->CHANCTRL[23U];
    
    
            
        }
    }
    
    
    #pragma CODE_STATE(vimParityErrorHandler, 32)
    #pragma INTERRUPT(vimParityErrorHandler, IRQ)
    #pragma WEAK(vimParityErrorHandler)
    
    /* SourceId : VIM_SourceId_006 */
    /* DesignId : VIM_DesignId_006 */
    /* Requirements : HL_SR105 */
    void vimParityErrorHandler(void)
    {
        uint32 vec;
        
        /* Identify the corrupted address */
        uint32 error_addr = VIM_ADDERR;
    
        /* Identify the channel number */
        uint32 error_channel = ((error_addr & 0x1FFU) >> 2U);
    
        if(error_channel >= VIM_CHANNELS)
        {
            /* Index is out of bonds */
            /* This condition should never be true since the HW only implements VIM_CHANNELS (96) channels */
            /* However, it was added due to defensive programming */
    /* USER CODE BEGIN (2) */
    /* USER CODE END */
        }
        else
        {
            /* Correct the corrupted location */
            vimRAM->ISR[error_channel] = s_vim_init[error_channel];
    
            /* Clear Parity Error Flag */
            VIM_PARFLG = 1U;
    
            /* Disable and enable the highest priority pending channel */
            if (vimREG->FIQINDEX != 0U)
            {
                vec = vimREG->FIQINDEX - 1U;
            }
            else
            {
               /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Read 32 bit volatile register" */
                vec = vimREG->IRQINDEX - 1U;
            }
            if(vec == 0U)
            {
                vimREG->INTREQ0 = 1U;
                vec = esmREG->IOFFHR - 1U;
    
                if (vec < 32U)
                {
                    esmREG->SR1[0U] = (uint32)1U << vec;
                    esmGroup1Notification(vec);
                }
                else if (vec < 64U)
                {
                    esmREG->SR1[1U] = (uint32)1U << (vec-32U);
                    esmGroup2Notification(vec-32U);
                }
                else if (vec < 96U)
                {
                    esmREG->SR4[0U] = (uint32)1U << (vec-64U);
                    esmGroup1Notification(vec-32U);
                }
                else
                {
                    esmREG->SR4[1U] = (uint32)1U << (vec-96U);
                    esmGroup2Notification(vec-64U);
                }
            }
            else if (vec < 32U)
            {
                vimREG->REQMASKCLR0 = (uint32)1U << vec;
                vimREG->REQMASKSET0 = (uint32)1U << vec;
            }
            else if (vec < 64U)
            {
                vimREG->REQMASKCLR1 = (uint32)1U << (vec-32U);
                vimREG->REQMASKSET1 = (uint32)1U << (vec-32U);
            }
            else
            {
                vimREG->REQMASKCLR2 = (uint32)1U << (vec-64U);
                vimREG->REQMASKSET2 = (uint32)1U << (vec-64U);
            }
        }
    }

  • Is there anyone who can help me?

  • The RTI timer is used for sampling ADC value and balancing the cell in TMS570 BMS TI Design:

    1. sample cells every 500 ms

    2. Balance target cell for 1 second, then relax for 3 seconds

    Please refer to the example code in this TI Design: http://www.ti.com/tool/TIDM-TMS570BMS?keyMatch=TI%20BMS%20DESIGN&tisearch=Search-EN-everything