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TMS570LC4357: DMA Current Destination Address

Tanay Ghose
Prodigy 180 points
Part Number: TMS570LC4357

Hi,

I am aware that from the CDADDR Register (Section 20.3.2.8, in TRM SPNU563a) it is possible to read the current destination address for DMA, ONLY IF a data transfer has been interrupted out of the priority queue, by a higher priority DMA Transfer.

Is there a method to find the current destination address, without creating such conflict between the channels ?

  • 0
    TI__Guru**** 197036 points

    Hi Tanay,

    The register is only updated after the condition in met. 

  • 0 in reply to QJ Wang
    Prodigy 180 points

    Thank you for your prompt response, Wang !

    On a related question for DMA, if it is not possible to determine Current Destination Address without arbitration, what happens if by chance the CPU reads from the same memory location that DMA is currently writing to ?

  • 0 in reply to Tanay Ghose
    TI__Guru**** 197036 points

    CPU will wait until the DMA transfer completes.

  • 0 in reply to Tanay Ghose
    TI__Mastermind 49120 points

    Tanay,

    Hercules device architecture is designed to minimize arbitration conditions like these. The CPU SRAM interconnect is designed such that an arbitration condition only exists if both the CPU and the DMA are accessing the same 64-bit address in the same cycle. In that rare case of the CPU and DMA (or other bus master) access the same 64-bit SRAM location in the same cycle, the read access will be delayed by one CPU clock cycle to allow the write access to complete first.

    Typically the available SRAM would be partitioned such that arbitration conditions like these do not occur. The DMA controller does provide several interrupt conditions that can be used to by the CPU to avoid running into the case you described: Frame Transfer Completed, Last Frame Transfer Started, Half Block Transfer Completed, and Block Transfer Completed.