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TMS570LC4357: Problem with MPU Settings for RAM and Flash

jinus zhang
Intellectual 340 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hello,

I am using mibspi + dma to do comunication between two LC4357 cores base on UCOS-3.

The MPU configuration of UCOS3 example project for TMS570LC4357HDK shows blow:

FLASH : NORMAL_OINC_NONSHARED

SRAM   : NORMAL_OINC_NONSHARED

To improve the CPU compute capacity I change the MPU settings for FLASH and SRAM as:

The test code execute time was greatly improved from 3.4ms to 0.6ms. But I got some questions:

1.Why DMA can still access SRAM when  SRAM  configed as NONSHARED (Conflict with MPU and Cache Settings in TMS570LC43x/RM57x Devices (SPNA238) says)?

2.Why config RAM as NOLMAL_OIWTNOWA_NONSHARED is more efficient than NOLMAL_OIWTNOWA_SHARED?

3.Why phantom Interrupt will generate, and  ACP D-Cache error from ESM module occurs?

4.How to config MPU modlue ？

Regards,

Jinus

  • 0
    TI__Guru**** 197166 points

    Hello Jinus,

    1. The "shared" or "non-shared" type does not affect concurrent accesses between CPU and DMA. This setting is to manage multiple CPUs accessing shared memory regions. The DMA has its own MPU in order to prevent spurious writes to memory regions based on addresses.

    2. Can you share your measurement? How big is the difference between nonshared and shared? Thanks

    3. Phantom interrupts occur when interrupt source cannot be determined. Please refer the application note written by one of TI MCU application engineer:   

    4. You can use HALCoGen to configure the MPU. Please refer the ARM TRM for using MPU: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460c/I1002400.html

  • 0 in reply to QJ Wang
    Intellectual 340 points

    Hello QJ,

    Thanks a lot.

    1. The "shared" or "non-shared" type does not affect concurrent accesses between CPU and DMA. This setting is to manage multiple CPUs accessing shared    memory regions. The DMA has its own MPU in order to prevent spurious writes to memory regions based on addresses.

    Thanks, I got it.

    2. Can you share your measurement? How big is the difference between nonshared and shared? Thanks

    Shared:1.9ms

    Nonshared:0.6ms

    3. Phantom interrupts occur when interrupt source cannot be determined. Please refer the application note written by one of TI MCU application

    I think the Scenario 2 accroing to SPNA063 is right explaination to the my Phantom Interrupt problem.

    At the end, the problem has been solved. The read-back code is needed after assign the value to REQMASKCLR3.

    (example project described in SPNA219)

    And my MPU configuration for RAM and Flash：

    FlASH : NORMAL_OIWTNOWA_NONSHARED

    SRAM  : NORMAL_OIWTNOWA_NONSHARED

    Why read-back is needed?

    4. Is there a Cache consistency problem with above configuration of SRAM when CPU and DMA both working. 

    Thanks and Regards,

    Jinus

  • 0 in reply to jinus zhang
    TI__Guru**** 197166 points

    1.  The OIWT means Outer/Inner Write-Through. You can ignore OI because this device doesn't have two levels of cache. Write through is important. There is write through and write back. Write through means when you write, if the data you write is in cached the cache gets updated but also the value in original memory (say L2SRAM) gets updated at the same time. This may slow you down a bit but helps if you are using DMA because the DMA cannot read data from cache.

    Write-back is faster because the writes only go to the main memory when there is a need to evict a line from cache. So it's a good type for your stack, global variables, etc. 

    WA is a policy that means if you don't have an address in the cache already because of a prior access, the first write itself will cause that line to be cached. These options are more important for the L2SRAM region (covering 0x0800 0000 to 0x0803 FFFF) where you have the RW attribute

    2. The Cortex-R5 ACP memory coherency scheme only provides coherency between an external master connected to the ACP slave port and a CPU with a data cache in the Cortex-R5 group for memory regions configured as inner cacheable write-through in the CPU’s MPU. It does not provide coherency for memory regions configured as cacheable write-back. The DMA doesn't use the cache at all.