TMS570LC4357-EP: System Exception Status Register: External Reset Flag and Debug Reset Flag

Charles Johnston

Part Number: TMS570LC4357-EP
Other Parts Discussed in Thread: HALCOGEN

Hello,

We are using a TMS570LC4357-EP with an XDS200 debugger. When debugging in Code Composer, if a CPU Reset and System Reset are performed, the MCU stops at 0x0000. The SysEsr register contains 0x00000808 which translates to an External Reset and a Debug Reset. The HALCoGen function getResetSource() returns an External Reset.

The Tech Ref Manual SPNU563 description of the System Exception Status Register does not include the new DBGRST as one of the resets that also asserts EXTRST.

Our external Watchdog chip is connected to nRST, so we need to know the difference.

Is EXTRST expected to be set when DBGRST is set?

Thanks you, Charlie Johnston

over 5 years ago

0 Sunil Oak over 5 years ago

TI__Mastermind 49120 points

Hi Charlie,

The nRST is a bi-directional signal, and is asserted (driven low) as output by the processor for any system reset condition, including a reset caused by the debugger (DBGRST). This causes EXTRST to be set for all system reset conditions, as explained in the reference manual SPNU563A. See section 2.3.1 on page 139 of this reference manual for more information.

The getResetSource function needs to be corrected to account for DBGRST causing EXTRST to also get set. You can use the "USER CODE" sections 25 and 26 to override the default HALCoGen generated function and write your own with the correct nested-if statement.

Regards, Sunil

0 Charles Johnston over 5 years ago in reply to Sunil Oak

Expert 2690 points

Hi Sunil,

Thank you for your quick response.

It looks like the getResetSource function also needs to be corrected to account for CPURST causing EXTRST to also get set.

Charlie Johnston

0 Sunil Oak over 5 years ago in reply to Charles Johnston

TI__Mastermind 49120 points

Hi Charlie,

CPU reset due to CPU self-test or by writing to CPURSTCR does not cause a system reset. So you can reset the CPU without causing the rest of the device to be reset. This part of the getResetSource is correct.

Regards, Sunil

0 Charles Johnston over 5 years ago in reply to Sunil Oak

Expert 2690 points

Hi Sunil,

I assumed a CPU reset would also set the External Reset bit since CPU reset is listed in TRM Section 2.3.1, Table 2-8.

Thanks, Charlie

0 Sunil Oak over 5 years ago in reply to Charles Johnston

TI__Mastermind 49120 points

Thanks Charlie.

We do need to exclude CPU Reset from the reset conditions that also drive nRST. I will enter the documentation feedback.

Regards, Sunil

0 Charles Johnston over 5 years ago in reply to Sunil Oak

Expert 2690 points

Thanks for your time, Sunil. You've been very helpful.

Charlie

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TMS570LC4357-EP: System Exception Status Register: External Reset Flag and Debug Reset Flag