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TMS570LS1114: Bit Multiplexing in Peripheral SRAM Memory Array

Arshad moilingal
Prodigy 200 points
Part Number: TMS570LS1114


Hello,

Here is the statement from safety manual for DCAN periheral,

DCAN SRAM is implemented with a bit multiplexing scheme such that the bits accessed to generate a logical (CPU) word are not physically adjacent. This scheme helps to reduce the probability of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest as multiple single bit faults.

My doubts are given belwo,

1. Would you explain what is the safety mechanism in module SRAM. Is it same as ECC? So far, I understood that there is no ECC in a module SRAM (e,.g; DCAN message SRAM area)

2. How can turn on this feature and how can i detect the fault and what mechanism need to be done so that diagnostic coverage can be make it high.

Best Regards,

Arshad Ziyad

 

 

 

  • 0
    TI__Guru**** 198766 points

    Hello,

    The bit mulitplexing has to do with the architecture of the RAM in relation to physical location of the bit cells. The CPU accesses the RAM in 64bit chunks. Within these 64bits, none of the bit cells are physically located adjacent to themselves in the RAM blocks. Because of this, if there is a disturbance from a cosmic event (radiation, alpha or beta particle) the likely hood of multi-bit faults within the 64-bit word is minimized. If a single bit is faulted, then it is corrected by the ECC logic so, in effect, the memory fault is avoided.

    The emphasis is that it is the physical layout of the RAM bit cells within the memory block that is the diagnostic.

    It is a fault avoidance mechanism and not categorized as a true diagnostic and. therefore, has no test for diagnostic. It is an architectural implementation of the RAM bit cells, and it is not a SW dependent mechanism that the application can disable or enable. This mechanism does not contribute to the overall diagnostic coverage of the device, it does impact the FIT rate calculations since the fault is avoided.