RM46L852: MibSPI Self Test Error Injection problems

Jinwook KIM

Prodigy 235 points

Part Number: RM46L852

Hello.

I'm trying to implement MIBSPI Self Test error injection according to Safety Manual Documents

Item is follow by:

1) BITERR

2) DLENERR

3) RXOVRN

But I have been able to successfully injection only BITERR Controls(There are some problem).

My code is following by ;

----------------------------------------------------------------------------------------------------------------------

{

................

mibspiREG1->LVL = (uint32)((uint32)0U << 9U) /* TXINT */
| (uint32)((uint32)0U << 8U) /* RXINT */
| (uint32)((uint32)0U << 6U) /* OVRNINT */
| (uint32)((uint32)0U << 4U) /* BITERR */
| (uint32)((uint32)0U << 3U) /* DESYNC */
| (uint32)((uint32)0U << 2U) /* PARERR */
| (uint32)((uint32)0U << 1U) /* TIMEOUT */
| (uint32)((uint32)0U << 0U); /* DLENERR */

mibspiREG1->FLG |= 0xFFFFU;

/** - enable interrupts */
mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFFFF0000U)
| (uint32)((uint32)0U << 9U) /* TXINT */
| (uint32)((uint32)0U << 8U) /* RXINT */
| (uint32)((uint32)1U << 6U) /* OVRNINT */
| (uint32)((uint32)1U << 4U) /* BITERR */
| (uint32)((uint32)0U << 3U) /* DESYNC */
| (uint32)((uint32)0U << 2U) /* PARERR */
| (uint32)((uint32)0U << 1U) /* TIMEOUT */
| (uint32)((uint32)1U << 0U); /* DLENERR */

..........

mibspiEnableLoopback(mibspiREG1,Digital_Lbk);

mibspiREG1->IOLPKTSTCR = mibspiREG1->IOLPKTSTCR | (uint32)((uint32)1 << 16U);

.......

mibspiDisableLoopback(mibspiREG1);

}

----------------------------------------------------------------------------------------------------------------------

void mibspi1HighLevelInterrupt(void)
{
uint32 mibspiFlags = (mibspiREG1->FLG & 0x0000FFFFU) & (~mibspiREG1->LVL & 0x035FU);
uint32 vec = mibspiREG1->INTVECT0;

/* USER CODE BEGIN (23) */
/* USER CODE END */

if (vec > 0x21U)
{
mibspiREG1->FLG = (mibspiREG1->FLG & 0xFFFF0000U) | mibspiFlags;
mibspiNotification(mibspiREG1, mibspiFlags & 0xFFU);
}
else
{
mibspiGroupNotification(mibspiREG1, ((vec & 0x3FU) >> 1U) - 1U);
}
/* USER CODE BEGIN (24) */
/* USER CODE END */
}

----------------------------------------------------------------------------------------------------------------------

void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (25) */

if((flag & (uint32_t)(1 << 0)) == (uint32_t)(1 << 0))
{
mibspiREG1->IOLPKTSTCR = mibspiREG1->IOLPKTSTCR & (uint32)~((uint32)1 << 16U);
(void)SerialPutString("\r\n A data length error has Occured!!!\r\n");
}

if(((flag >> 4) & 0x00000001) == 0x00000001)
{
mibspiREG1->IOLPKTSTCR = mibspiREG1->IOLPKTSTCR & (uint32)~((uint32)1 << 20U);
(void)SerialPutString("\r\n A bit Error has Occured!!!\r\n");
}

if((flag & (uint32_t)(1 << 6)) == (uint32_t)(1 << 6))
{
(void)SerialPutString("\r\n Overrun condition Error has Occured!!!\r\n");
}

/* USER CODE END */
}

----------------------------------------------------------------------------------------------------------------------

Result is :

1. BITERR : Interrupt occurs twice but incoming interrupt.

2. DLENERR : Can't get anything (No Iterrupt)

3. RXOVRN : I don't know how to loopback test.

That's it.

Looking forward to response these.

Thank you.

Gene.

Thank you

over 5 years ago

0 Jinwook KIM over 5 years ago

Prodigy 235 points

There is a missing part.

-----------------------------------------------------------------------------------------------------------------------

..............

mibspiEnableLoopback(mibspiREG1,Digital_Lbk);

mibspiREG1->IOLPKTSTCR = mibspiREG1->IOLPKTSTCR | (uint32)((uint32)1 << 16U); // DLENERR loopback test set

mibspiREG1->IOLPKTSTCR = mibspiREG1->IOLPKTSTCR | (uint32)((uint32)1 << 20U); // BITERR loopback test set

..............

-----------------------------------------------------------------------------------------------------------------------

Thank you.

0 QJ Wang over 5 years ago in reply to Jinwook KIM

TI__Guru**** 192486 points

Hello,

Only the errors listed in IOLPBKSTCR register can be induced. RXOVRN is not included.

To get DESYNC error, the SPIENA should be configured as functional pin.

0 Jinwook KIM over 5 years ago in reply to QJ Wang

Prodigy 235 points

Hello, Wang.

Thank you for your reply.

Unfortunately, I didn't get Error Injection result for DLENERR.

It didn' t occur Interrupt in Loopback test.

Can i get a example for DLENERR Injection in Loop back test mode?

My MIBSPI Register set is follow by: - It's too long ;)

----------------------------------------------------------------------

void mibspiInit(void)
{
uint32 i ;

/* USER CODE BEGIN (2) */
/* USER CODE END */

/** @b initialize @b MIBSPI1 */

/** bring MIBSPI out of reset */
mibspiREG1->GCR0 = 0U;
mibspiREG1->GCR0 = 1U;

/** enable MIBSPI1 multibuffered mode and enable buffer RAM */
mibspiREG1->MIBSPIE = (mibspiREG1->MIBSPIE & 0xFFFFFFFEU) | 1U;

/** MIBSPI1 master mode and clock configuration */
mibspiREG1->GCR1 = (mibspiREG1->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */
| 1U); /* MASTER */

/** MIBSPI1 enable pin configuration */
mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */

/** - Delays */
mibspiREG1->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */
| (uint32)((uint32)0U << 16U) /* T2CDELAY */
| (uint32)((uint32)0U << 8U) /* T2EDELAY */
| (uint32)((uint32)0U << 0U); /* C2EDELAY */

/** - Data Format 0 */
mibspiREG1->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)0U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)109U << 8U) /* baudrate prescale */
| (uint32)((uint32)8U << 0U); /* data word length */

/** - Data Format 1 */
mibspiREG1->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)1U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)109U << 8U) /* baudrate prescale */
| (uint32)((uint32)8U << 0U); /* data word length */

/** - Data Format 2 */
mibspiREG1->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)0U << 17U) /* clock polarity */
| (uint32)((uint32)1U << 16U) /* clock phase */
| (uint32)((uint32)109U << 8U) /* baudrate prescale */
| (uint32)((uint32)8U << 0U); /* data word length */

/** - Data Format 3 */
mibspiREG1->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)1U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)109U << 8U) /* baudrate prescale */
| (uint32)((uint32)16U << 0U); /* data word length */

/** - Default Chip Select */
mibspiREG1->DEF = (uint32)(0xFFU);

/** - wait for buffer initialization complete before accessing MibSPI registers */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((mibspiREG1->FLG & 0x01000000U) != 0U)
{
} /* Wait */

/** enable MIBSPI RAM Parity */
mibspiREG1->UERRCTRL = (mibspiREG1->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U);

/** - initialize transfer groups */
mibspiREG1->TGCTRL[0U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)0U << 8U); /* start buffer */

mibspiREG1->TGCTRL[1U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)1U << 8U); /* start buffer */

mibspiREG1->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(1U+0U) << 8U); /* start buffer */

mibspiREG1->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(1U+0U+0U) << 8U); /* start buffer */

mibspiREG1->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(1U+0U+0U+0U) << 8U); /* start buffer */

mibspiREG1->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(1U+0U+0U+0U+0U) << 8U); /* start buffer */

mibspiREG1->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(1U+0U+0U+0U+0U+0U) << 8U); /* start buffer */

mibspiREG1->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(1U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */

mibspiREG1->TGCTRL[8U] = (uint32)(1U+0U+0U+0U+0U+0U+0U+0U) << 8U;

mibspiREG1->LTGPEND = (mibspiREG1->LTGPEND & 0xFFFF00FFU) | (uint32)((uint32)((1U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);

/** - initialize buffer ram */
{
i = 0U;

#if (1U > 0U)
{

#if (1U > 1U)

while (i < (1U-1U))
{
mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)1U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)2U << 8U) /* data format */
/*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
| ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */
i++;
}
#endif
mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)2U << 8U) /* data format */
/*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
| ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((1U+0U)-1U))
{
mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
/*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
| ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif
mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 8U) /* data format */
/*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
| ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((1U+0U+0U)-1U))
{
mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)1U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
/*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
| ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((1U+0U+0U+0U)-1U))
{
mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)1U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
/*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
| ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((1U+0U+0U+0U+0U)-1U))
{
mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)1U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
/*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
| ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((1U+0U+0U+0U+0U+0U)-1U))
{
mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)1U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
/*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
| ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((1U+0U+0U+0U+0U+0U+0U)-1U))
{
mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
/*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
| ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((1U+0U+0U+0U+0U+0U+0U+0U)-1U))
{
mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
/*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
| ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */

/** - set interrupt levels */
mibspiREG1->LVL = (uint32)((uint32)0U << 9U) /* TXINT */
| (uint32)((uint32)0U << 8U) /* RXINT */
| (uint32)((uint32)0U << 6U) /* OVRNINT */
| (uint32)((uint32)0U << 4U) /* BITERR */
| (uint32)((uint32)0U << 3U) /* DESYNC */
| (uint32)((uint32)0U << 2U) /* PARERR */
| (uint32)((uint32)0U << 1U) /* TIMEOUT */
| (uint32)((uint32)0U << 0U); /* DLENERR */

/** - clear any pending interrupts */
mibspiREG1->FLG |= 0xFFFFU;

/** @b initialize @b MIBSPI1 @b Port */

/** - MIBSPI1 Port output values */
mibspiREG1->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)1U << 3U) /* SCS[3] */
| (uint32)((uint32)1U << 4U) /* SCS[4] */
| (uint32)((uint32)1U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)0U << 9U) /* CLK */
| (uint32)((uint32)0U << 10U) /* SIMO[0] */
| (uint32)((uint32)0U << 11U) /* SOMI[0] */
| (uint32)((uint32)0U << 17U) /* SIMO[1] */
| (uint32)((uint32)0U << 25U); /* SOMI[1] */

/** - MIBSPI1 Port direction */
mibspiREG1->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)1U << 3U) /* SCS[3] */
| (uint32)((uint32)1U << 4U) /* SCS[4] */
| (uint32)((uint32)1U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)1U << 9U) /* CLK */
| (uint32)((uint32)1U << 10U) /* SIMO[0] */
| (uint32)((uint32)0U << 11U) /* SOMI[0] */
| (uint32)((uint32)0U << 17U) /* SIMO[1] */
| (uint32)((uint32)0U << 25U); /* SOMI[1] */

/** - MIBSPI1 Port open drain enable */
mibspiREG1->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */
| (uint32)((uint32)0U << 1U) /* SCS[1] */
| (uint32)((uint32)0U << 2U) /* SCS[2] */
| (uint32)((uint32)0U << 3U) /* SCS[3] */
| (uint32)((uint32)0U << 4U) /* SCS[4] */
| (uint32)((uint32)0U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)0U << 9U) /* CLK */
| (uint32)((uint32)0U << 10U) /* SIMO[0] */
| (uint32)((uint32)0U << 11U) /* SOMI[0] */
| (uint32)((uint32)0U << 17U) /* SIMO[1] */
| (uint32)((uint32)0U << 25U); /* SOMI[1] */

/** - MIBSPI1 Port pullup / pulldown selection */
mibspiREG1->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)1U << 3U) /* SCS[3] */
| (uint32)((uint32)1U << 4U) /* SCS[4] */
| (uint32)((uint32)1U << 5U) /* SCS[5] */
| (uint32)((uint32)1U << 8U) /* ENA */
| (uint32)((uint32)1U << 9U) /* CLK */
| (uint32)((uint32)1U << 10U) /* SIMO[0] */
| (uint32)((uint32)1U << 11U) /* SOMI[0] */
| (uint32)((uint32)1U << 17U) /* SIMO[1] */
| (uint32)((uint32)1U << 25U); /* SOMI[1] */

/** - MIBSPI1 Port pullup / pulldown enable*/
mibspiREG1->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */
| (uint32)((uint32)0U << 1U) /* SCS[1] */
| (uint32)((uint32)0U << 2U) /* SCS[2] */
| (uint32)((uint32)0U << 3U) /* SCS[3] */
| (uint32)((uint32)0U << 4U) /* SCS[4] */
| (uint32)((uint32)0U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)0U << 9U) /* CLK */
| (uint32)((uint32)0U << 10U) /* SIMO[0] */
| (uint32)((uint32)0U << 11U) /* SOMI[0] */
| (uint32)((uint32)0U << 17U) /* SIMO[1] */
| (uint32)((uint32)0U << 25U); /* SOMI[1] */

/* MIBSPI1 set all pins to functional */
mibspiREG1->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */
| (uint32)((uint32)0U << 1U) /* SCS[1] */
| (uint32)((uint32)0U << 2U) /* SCS[2] */
| (uint32)((uint32)0U << 3U) /* SCS[3] */
| (uint32)((uint32)0U << 4U) /* SCS[4] */
| (uint32)((uint32)0U << 5U) /* SCS[5] */
| (uint32)((uint32)1U << 8U) /* ENA */
| (uint32)((uint32)1U << 9U) /* CLK */
| (uint32)((uint32)1U << 10U) /* SIMO[0] */
| (uint32)((uint32)1U << 11U) /* SOMI[0] */
| (uint32)((uint32)1U << 17U) /* SIMO[1] */
| (uint32)((uint32)1U << 25U); /* SOMI[1] */

/** - Finally start MIBSPI1 */
mibspiREG1->GCR1 = (mibspiREG1->GCR1 & 0xFEFFFFFFU) | 0x01000000U;

/* USER CODE BEGIN (3) */
/* USER CODE END */

}

----------------------------------------------------------------------

Looking forward to reply soon.

Best regards.

Gene.

0 QJ Wang over 5 years ago in reply to Jinwook KIM

TI__Guru**** 192486 points

Hello Gene,

Here is my test. The error flag in SPIFLG is 0x01 --> DLENERRFLG

Arm-based microcontrollers

Arm-based microcontrollers forum

RM46L852: MibSPI Self Test Error Injection problems