EK-TM4C1294XL: TM4C ADC offset calibration

Gl said:

How can TM4C1294 ADC channels be offset calibrated for 0V near VDDA.

If you are asking how to calibrate for an input range from near VDDA to above VDDA then they cannot. I've not run into any A/D that could do that.

If that's not what you are asking then you need to clarify the question.

Gl said:

For instance two channel steps (same 2 sensor part #'s) require very different filter math to get ambient temperatures to calibrate equally. This seems directly related to analog channel FIFO values being widely offset from 0V 1LSB counts. 

Just what do you expect from an A/D? Your implied expectations seem well beyond mine, especially for an A/D embedded in a micro.

Robert

Hi Mr. Adsett1,

This link to original post was originally put in this forum but was moved for what ever reason. Learning a few new things venturing beyond the tide and true.

That was not the link I was thinking of but has the SW to do ADC offset calibration for 12 bit SAR ADC's.  

https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/892157

13.13.1 ADC Zero Offset Calibration

Zero offset error is defined as the difference from 0 that occurs when converting a voltage at VREFLO. The zero offset error can be positive or negative. To correct this error, an adjustment of equal magnitude and opposite polarity is written into the ADCOFFTRIM register. The value contained in this register will be applied before the results are available in the ADC result registers. This operation is fully contained within the ADC core, so the timing of the results will not be affected and the full dynamic range of the ADC will be maintained for any trim value.

Using the GetAdcOffsetTrimOTP(Uint16) function, the ADCOFFTRIM register can be loaded with the factory calibrated offset error correction. The user can modify the ADCOFFTRIM register to compensate for additional offset error induced by the application environment if desired, but this is not typically necessary to achieve datasheet specified performance.

NOTE: Regardless of the converter resolution, the size of each ADCOFFTRIM step is (VREFHIVREFLO)/65536.

Use the following procedure to re-calibrate the ADC offset in 12-bit, single-ended mode:
1. Set ADCOFFTRIM to +112 steps (0x70). This adds an artificial offset to account for negative offset that may reside in the ADC core.
2. Perform some multiple of 16 conversions on VREFLO (internal connection), accumulating the results (for example, 32*16 conversions = 512 conversions).
3. Divide the accumulated result by the multiple of 16 (for example, for 512 conversions, divide by 32).
4. Set ADCOFFTRIM to 112 – result from step 3.

Though after solder paste reflow oven temperatures and what was the ambient room temp ADC was factory calibrated? All are expected to take the blue light lane sales pitch as gospel. Yet the kits channel offsets were uneven from internal PGA amplifiers output into 3 ADC's as kelvin shunt current monitors.

I'd bet there is some way to do the same kind of calibration for TM4C1294/123 ADC's and it was never revealed in datasheet. Perhaps some other method can achieve the same basic zero offset calibration, was thought of posting.

Gl said:

This link to original post was originally put in this forum but was moved for what ever reason. Learning a few new things venturing beyond the tide and true.

I read it when it was originally posted. It wasn't sufficiently clear to even attempt to parse what you wanted to ask.

Robert

Gl said:

Perhaps some other method can achieve the same basic zero offset calibration, was thought of posting.

By applying an offset and scale as most people do perhaps?

Robert

Robert Adsett1 said:

It wasn't sufficiently clear to even attempt to parse what you wanted to ask.

Like anything new what you have never seen or heard of seems alien unknown. Imagine what aliens might look like, Spock's pointed ears wins hands down! Now where did I put those extra Di-lithium crystals.

Robert Adsett1 said:

By applying an offset and scale as most people do perhaps?

See how C2000 has a register to store the derived offset value, so the ADC must set 1LSB to that register value? Was hoping TI troops may have some ideas when they return. Have you noticed too that sequencer steps or channels for those steps are not so consistent in the TM4C123? Did you ever get EK1294 launch pad to test with?