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TMS570LS3137: emif_clk result CPU Reset

Alban yang
Intellectual 300 points
Part Number: TMS570LS3137

Hi,

I use tms570ls3137 emif module, it was connected with FPGA. There is one question that it is Asynchronus interface, generally it don't need using emif_clk pin. So it happen _dabort when I diable VCLK3 domain. If I enable VCLK3 domain, it will result cpu reset or couldn't start. I want to know whether must to be used emif_clk pin. Thanks very much.  

  • 0
    TI__Guru**** 197166 points

    Hello Alban,

    The VCLK3 has to be enabled to make EMIF module work. The EMIF_CLK is driven from VCLK3. The EMIF control signals are generated based on EMIF_CLK even though the EMIF_CLK is not used by the external async memory.

    I am not sure if FPGA needs a clock from MCU as a reference sync clock or not.

  • 0 in reply to QJ Wang
    Intellectual 300 points

    Hello QJ,

    Thanks for your answer. I met one issue that the emif module result CPU reset. I don't know why reason. It happened reset when I disable AWCC Init and page mode change where there is in emif2 Init. I don't know why result in cup reset.

  • 0 in reply to Alban yang
    TI__Guru**** 197166 points

    Hello,

    AWCC is to select EMIF Wait signal, and PMCR is only for NOR flash. Is the CPURST bit in the SYSESR set after reset? Is there any signal on FPGA which can pull-down nRST or nPORRST?

    The CPU reset can be asserted by:

    1. CPU self-test (LBIST)

    2. toggle bit 0 of CPURSTCR register

    3. CPU Interconnect Subsystem self test.