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TMS570LS3137: Workaround Errata FMC#80 Abort on Accesses Switching Between two Banks

_MM_
Expert 1995 points
Part Number: TMS570LS3137


Hello,

I cannot understand how to implement the workaround described in the spnz195g document. I have HCLK to 180 MHz and I cannot decrease it and I guess that it operates always in single-cycle mode, correct? 

  • 0
    TI__Mastermind 49120 points

    This issue only applies if you are not enabling additional wait states for accesses to Flash memory. Before switching CPU clock to 180MHz the flash access wait states must be set as per the datasheet requirements. In this case the issue does not apply.

    Regards, Sunil