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Original question:

CCS/TMS570LC4357: Issue in Flash programming using F021 Flash library.

CCS/TMS570LC4357: Issue with flash programming, how to configure cache?

Simon W
Prodigy 110 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

Hi,

my question is related to this thread: https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/577279

I'm using F021 Flash API v2.01.01 Build(000830) and I'm experiencing kind of the same issue as described in the thread mentioned above. After erasing a sector and programming data, validating the programmed data fails.
What I do is:

  1. Erase a sector
  2. Program data
  3. Validate data, i.e. read data from flash and compare with programmed data. Result: data is equal
  4. Erase the same sector again
  5. Program different data
  6. Validate data. Result: data is not equal, although it should be equal (in the memory browser it also seems like the newly programmed data is hidden)

When I do it according to Christian's suggestion (see thread mentioned above) and simply call _dCacheInvalidate_(); after programming, it works as expected (the newly programmed data shows up and validation is successful). Probably using Christian's "new cache maintenance function" would work as well but I haven't tried it yet.

I tried to solve this issue in different ways but none of them seems to be a clean solution:

  • Call _dCacheInvalidate_(); after writing data to the flash
  • In the HalCoGen MPU tab: Disable the cache
  • In the HalCoGen MPU tab: Set flash memory region type to "NORMAL_OINC_NONSHARED" (Memory type normal outer and inner non-cachable and non shared)

I also read your application report on MPU and cache settings (http://www.ti.com/lit/an/spna238/spna238.pdf). As far as I understand, what I need is that data is written to the flash memory even for write accesses that are cache-hit. From my understanding it should be sufficient to configure the flash memory region type as "NORMAL_OIWTNOWA_NONSHARED" (Memory type normal outer and inner write-through non write allocate and non shared). Could you please explain why that doesn't work and how would a clean solution for that problem look like?

Thanks for your help,

Simon

  • 0
    TI__Guru**** 199096 points

    Hello Simon,

    The MPU setting (WT or WB) for flash does affect the data programmed to the flash. But when reading data from flash, the CPU will check the cache first, then the SRAM if the data is not in the cache.

    You read the flash content at 0x220000 after erase operation, then read it again after program operation. The returned value is always 0xffffffff.

  • 0 in reply to QJ Wang
    TI__Guru**** 199096 points

    Hello Simon,

    I will do test today and come back to you later.

  • 0 in reply to QJ Wang
    Prodigy 110 points

    Hello QJ,

    Thank you for your help.
    Regarding your first answer I wanted to mention that after programming for the first time, the data that I read is correct and it is not 0xffffffff. Additionally the "MPU and Cache Settings Application Report" (SPNA238) points out that:

    "If an access to a cached, non-shared normal memory is performed, cache controller does a lookup in the cache table. If the location is already present in the cache, that is a cache hit, the data is read from or written to the cache."

    That means whenever I try to write data to the flash memory, data is always written to the cache no matter if write-through or write-back is selected. So if the CPU first checks the cache (as you mentioned), I should always get the data that just has been written.
    Thanks again.

    Kind regards,

    Simon

  • 0 in reply to Simon W
    TI__Guru**** 199096 points

    Hi Simon,

    The flash write is performed by the flash state machine rather than the CPU, the data is written to flash wrapper registers, then programmed to the flash. So the data is always written to the flash. You can use JTAG DAP to check the flash memory.

    The cacheable or non-cacheable setting of flash memory region does affect flash read. When cahce hit occurs, the data in cache instead of from flash is read out. 

  • 0 in reply to QJ Wang
    Prodigy 110 points

    Hello QJ,

    Thanks again.
    What does that mean, in the end and how can I solve my problem?

    Does it mean that if I read and modify data in the flash several times, I have to either use the non-cacheable setting or invalidate the cache in order to make sure that I always get the data that is currently programmed into the flash?

    Thank you and regards,

    Simon

  • 0 in reply to Simon W
    TI__Guru**** 199096 points

    Hello Simon,

    You are correct. 

    The 1st solution is to configure this region as "shared" or "non-cacheable" to prevent this region from being cached in DCache.

    The 2nd solution is to clean or invalidate cache before flash reading operation