TM4C123GH6PM: ADC

In that case it will not make an eighth conversion for that sequence, it will only make 5. If 8 different samples are desired for that sequence, then the END bit should only be set for the the eighth step. But don't confuse the number of samples with the FIFO depth. Sequence 0 also has a FIFO depth of 8. If you configure the sequence for 5 samples, and get another trigger (restart the sequence) before you read any of the values from the FIFO, it will continue to fill until the FIFO is full with eight values.

Are you asking these details out of curiosity, or are you trying to figure out how to setup the ADC converter? If it is the latter, you should use the TivaWare driver library provided by TI. This simplifies the register details. There is an advanced example in C:\ti\TivaWare_C_Series-2.2.0.295\examples\boards\ek-tm4c123gxl\adc_udma_pingpong that shows configuring the timer to periodically start the ADC and the DMA to read the results and store them in RAM. The steps of the sequence are configured with calls to the function ADCSequenceStepConfigure(). To configure sequence 0 to convert AIN0, AIN1 and AIN2 would look like this:

    ADCSequenceStepConfigure(ADC0_BASE, 0, 0, ADC_CTL_CH0 );
    ADCSequenceStepConfigure(ADC0_BASE, 0, 1, ADC_CTL_CH1 );
    ADCSequenceStepConfigure(ADC0_BASE, 0, 2, ADC_CTL_CH2 | ADC_CTL_END | ADC_CTL_IE);

Note that the attribute ADC_CTL_END is only set for the last step. Also I chose to enable an interrupt request after the channel 2 conversion completes.

When not using DMA, reading from the FIFO is done with the function ADCSequenceDataGet(). This function, and other TivaWare functions, are described in: C:\ti\TivaWare_C_Series-2.2.0.295\docs\SW-TM4C-DRL-UG-2.2.0.295.pdf. It reads all of the values in the FIFO storing them in a buffer you provide. It returns the number of entries read. You don't need to keep track of FIFO pointers. A call to the function ADCSequenceOverflow() will tell you if there was a FIFO overflow.