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CCS/TMS570LC4357: Is it possible to use lwIP+FreeRTOS on TMS570LC4357 HDK Board

Part Number: TMS570LC4357

Tool/software: Code Composer Studio

Hi all,

Our reasons for choosing Texas Instruments are strong support community and quality products. But we see that it is not available for TMS570LC4357.

I started following three question below. I am asking and trying to you day and day. But there is even no answer. I have been waiting for 30 days.

CCS/TMS570LC4357: Light lwIP project pinging on my HDK but lwIP+FreeRTOS Project has a ping problem.
Link 1 : https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/901249

CCS/TMS570LC4357: lwIP+FreeRTOS Project Ping Problem
Link 2 : https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/896341

CCS/TMS570LC4357: TMS570LC4357 FreeRTOS + lwIP Project Error
Link 3 : https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/893613

 

Let me tell you before you answer:

 

I am aware of this post : 

https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/799670?RTOS-TMS570LC4357-How-can-i-use-to-lwIP-at-RTOS

And this example supported by Texas Instruments Guru  : 

7178.TMS570LC4357_FreeRTOS_LWIP.7z

 

Although server succesfully initialized linked example above did not ping. Also I know MPU setting must be write through. I tried everything.

So please do not tell me " you should change MPU setting from cache write-back to cache write-through".

I only want to know something. Is it possible to use lwIP+FreeRTOS in same project with network functions like multicast,unicast for the data transmission?

Are there any hardware level restrictions to do this successfully?

 

If I can do it, I will use TMS570LC4357 HDK system for a part of a data communication based infructruture . And you will be able to sell lots of TMS570LC4357 HDK to me. Why don't you choose help me?

Thanks and Regards,

  • Hello,

    There is no HW level restriction for freeRTOS+LWIP to execute on HDK or Launchpad. You have tested lwip and freeRTOS separately, and knew that they works very well. The only issue is caused by the cache coherency between CPU and EMAC DMA.

    By default, freeRTOS configures all the RAM regions as cacheable (write-back, write-through) for better performance. This configuration is not suited in case multiple bus masters access the RAM, for example, DMA or EMAC master. This is why I mentioned MPU settings several times. As I mentioned, I don't have HW (HDK) to do this test at home. 

  • Hi Dear QJ Wang,

    Let's take a positive look at the situation, you are so lucky to be able to run your bussiness at home in COVID-19 days.

    Stay healty and prosperous :)

    Thanks and Regards,