RM46L852: Data loss on SPI using CAN bus concurrently

Hello Oliver,

Do you mean AM43x sends the same data to RM48x through MibSPI1 and CAN1? How many data is lost when use SPI and CAN at same time? How do you configure the MibSPI Buffer? Do you use polling mode or interrupt mode for CAN receive and MibSPI receive?

Did you probe the MibSPI_SIMO signal bus to check if the data is transmitted correctly?

Hi,

I try to describe the things more clearly:

1. For data transferred from the master to the slave data words are just missing in the input buffer.
2. For data transferred from the slave to the master data words are corrupted. We observed that in the error situation the Hercules MISO pin gets high-impedance. As this does happen with a certain slew rate the words are often corrupted in a way that they are 0x7FFF.
3. If we do the same WITHOUT using the CAN concurrently everything is fine.
4. The respective CAN-Bus is also connected to the AM43x but the the transferred data is different and has no relation to the data exchanged via SPI.
5. We get the identical errors if we just read during the SPI transfer the memory of a currently unused SPI transfer group on the Hercules so we rather get the impression that the problem arises from accessing the SRAM of a peripheral.
6. On the RM46x interrupts are disabled for SPI as well as CAN (Polling mode only).

I hope this description provides a better look on what we are doing.

Best regards,

  Oliver

Hi Oliver,

During a transfer, if the SPI slave (RM46) detects a de-assertion of SPICS before its internal character length counter overflows, then it places SPISOMI in high-impedance mode. 

Hi QJ,

we checked that CS is always asserted during the complete transmission and it is not the SPISOMI which changes into high-impedance but the SPIMISO (and RM46 is slave).

We have no problems exchanging SPI data if we do not use the CAN or read the memory of an unused SPI transfer group. So there is still our assumption that accessing concurrently SRAM of the same or another peripheral unit (with the CPU) while MibSPI1 tries to read and/or store data from it's own SRAM (in background) leads to a situation where the SPI unit has to discard received data or cannot provide valid transmit data as it is unable to access to its own SRAM in time.

Best regards,

  Oliver

Hello,

MibSPI RAM can only be access by CPU, DMA and SPI state machine. MibSPI buffer should not be affected by CAN message. Can you please share your code with us?

Hi QJ,

as one need a SPI master and an additional CAN node to reproduce the issue the team will try to write some test code which is using the Hercules loopback communication capabilities. As there are currently a lot of other project tasks to complete I assume I can come back to you at the beginning of next week with results about our progress.

Best regards,

  Oliver

Thanks Oliver