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RM46L852: Reset behaviour

Oliver Thimm
Intellectual 280 points

Part Number: RM46L852
Other Parts Discussed in Thread: HALCOGEN

Hello,

I'm looking for some clarification about the (warm) reset behavior of the RM46. In the technical reference manual for each register the state after reset is documented. Some register are persistent in case of a reset what is also documented. I wonder if

  1. This documented state after reset is applicable for cold as well as for warm reset if not documented different or if the document only describes the state after a cold reset.
  2. The CPU reset is different from other (warm) reset reasons like PLL slip, Watchdog, etc. as it seems in the code generated by HALCoGen that after a self-test of CPU STC and CPU the code continues calling afterSTC() without an additional call to eg. systemInit() so I assume that no registers outside the CPU core are affected by a CPU reset ?

Best regards,

  Oliver

  • 0
    TI__Mastermind 49120 points

    Hi Oliver,

    The TRM register description includes the bit-field reset values. This typically refers to warm reset (system reset). Any bit-field that is only reset by cold reset (power-on-reset) is explicitly specified as such. For example, ESM status registers are only reset by cold reset.

    CPU reset is indeed separate from system reset, and only resets the CPU.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Intellectual 280 points

    Hi Sunil,

    thank you very much for this fast response which answered all my questions to the reset behavior and the documentation on it.

    Best regards,

      Oliver