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TMS570 avionics SEU statistics

Hello.

In accordance to that TMS570 is recommended for use in such safety-critical systems as avionics, are there any single event upsets (SEU) statistics or bit error rates available for TMS570 RAM and core registers?

Does the TMS570 Cortex-R4 lock-step mode with ECC functions enabled on RAM and flash completely prevent SEU effects?

Thanks, Evgenyy.

  • Hello,

    Information on SEU statistics and error rates is available for the TMS570LS family as part of our safety deliverable package.  This information is available under NDA.  Please contact your local TI sales office to set up an NDA or to recieve the safety deliverables once under NDA.

     

    Best Regards,

    Karl