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TM4C1294NCPDT: Is it safe to switch clock during operation?

David Chance
Genius 4775 points
Part Number: TM4C1294NCPDT


I have an application that I need to switch the master clock, say from 25Mhz to 24Mhz, back and forth during operation. I can include both oscillators on the design, but it is safe to use GPIO to switch between them? At the moment of the switch, there will be a disruption in clock pulses, and good chance it will be a sharp pulse way higher than 25Mhz.

Thanks for any pointer!

  • 0
    TI__Guru**** 191906 points

    Hi David,

      Why would your application require switching between two different oscillators? How are you going to synchronize the GPIO switching with the oscillators. To me, it is not a good idea at all to do what you describe. Wouldn't all the baud rates in your communication peripherals thrown off? Yes, the sharp pulse on the clock can trip the oscillator fail detection. If you are using the PLL, the PLL may lose lock too. I will suggest you stay with only one oscillator input.

  • 0 in reply to Charles Tsai
    Genius 4775 points

    In this specific operation, there is no communication peripheral going on during the switch.

    Do this condition allow safe switching between two clock sources?

  • 0 in reply to David Chance
    TI__Guru**** 191906 points

    Hi,

      Even if you don't have communication peripherals going on during this 'asynchronous' clock switching, you still have the risk to trip the MOSC fail detection and PLL losing lock. 

  • 0 in reply to Charles Tsai
    Genius 4775 points

    what is the worst result of "trip the MOSC fail detection and PLL losing lock" for a moment?

  • 0 in reply to David Chance
    TI__Guru**** 191906 points

    HI,

      The device can reset. Please see below from the datasheet.

    5.2.3.2 Main Oscillator Verification Failure
    The TM4C1294NCPDT microcontroller provides a main oscillator verification circuit that generates
    an error condition if the oscillator is running too fast or too slow. If the main oscillator verification
    circuit is enabled and a failure occurs, either a power-on reset is generated and control is transferred
    to the NMI handler, or an interrupt is generated. The MOSCIM bit in the MOSCCTL register determines
    which action occurs. In either case, the system clock source is automatically switched to the PIOSC.
    If a MOSC failure reset occurs, the NMI handler is used to address the main oscillator verification
    failure because the necessary code can be removed from the general reset handler, speeding up
    reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator
    Control (MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator
    fail status (MOSCFAIL) bit in the Reset Cause (RESC) register. The main oscillator verification circuit
    action is described in more detail in the section called “Main Oscillator Verification Circuit” on page 236.

    PLL Operation
    If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
    to the new setting. The time between the configuration change and relock is TREADY (see Table
    27-16 on page 1835). During the relock time, the affected PLL is not usable as a clock reference.
    Software can poll the LOCK bit in the PLL Status (PLLSTAT) register to determine when the PLL
    has locked.
    Modification of the PLL VCO frequency may not be performed while the PLL serves as a clock
    source to the system. All changes to the PLL must be performed using a different clock source until
    the PLL has locked frequency. Thus, changing the PLL VCO frequency must be done as a sequence
    from PLL to PIOSC/MOSC and then PIOSC/MOSC to new PLL.