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Compiler/TMS570LC4357: RAM module details on Cortex R4F and R5F

Shivam Kakad
Expert 1355 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: TMS570LS3137

Tool/software: TI C/C++ Compiler

Hi Team,

The TMS570LS3137 device is built around ARM Cortex R4F CPU whereas the TMS570LC4357 uses ARM CortexR5F CPU.

As per the reference manual of both the device the RAM module used for the 3137 is TCRAM(256 kb), which internally composed of the ATCM and BTCM which further divided into even and odd.

and for the 4357, the RAM module is L2RAMW(512 kb) which is not divided among even and odd as it was there in the TCRAM.

I am bit confused with this two different naming convention and even the register fields for this two devices are different.

Could you help me in understanding this RAM modules for the different devices. How it is different for the 4357 than 3137. What are the advantages/disadvantages for having this two different modules for this two different CPU?

Regards,

Shivam

  • 0
    TI__Mastermind 49120 points

    Hi Shivam,

    The TMS570LSx and TMS570LCx parts use two separate architectures for connecting the CPU RAM, as you have correctly also identified.

    TMS570LSx parts:

    These parts use the ARM Cortex-R4(F) processor with the CPU RAM connected as a tightly-coupled memory (TCM). You can get a more detailed understanding of what "tightly-coupled memory" means from the ARM Architecture Reference Manual (ARM ARM). The R4 CPU supports two tightly-coupled memory interfaces, named ATCM and BTCM.

    ATCM is used to connect the main Flash memory for storing instructions and data.

    BTCM is used to connect the CPU RAM. This interface is made up of two separate interfaces: B0TCM and B1TCM. These are 64-bit interleaved, meaning that 64-bit addresses 0x08000000 + (N * 0x08) are accesses to B0TCM for N = 0, 2, 4, 6, ... and are accesses to B1TCM for N = 1, 3, 5, 7, ...

    This is done specifically to minimize arbitration requirement between multiple bus masters accessing the CPU RAM at the same time. As long as multiple bus masters do not access the same 64-bit location, there is no need for any arbitration and both accesses can happen in parallel.

    TMS570LC4357:

    This part uses the ARM Cortex-R5F processor. This part uses a cached-CPU architecture (32KB caches for instruction and data) to support the higher operating frequency of the CPU (up to 300MHz). The tightly-coupled memory interfaces are not used on this part, so ATCM and BxTCM are not available.

    The main program memory (4MB Flash) and SRAM (512KB) are connected as level 2 memories on this part. This means that the CPU accesses that miss in the cache have to go through the first level of the main interconnect to get to the program memory or data. This is the cache miss penalty. Any cache miss causes the cache to be refilled with instructions / data from the "new" location that was just fetched from the level 2 memory.

    Hope this helps.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Expert 1355 points

    Thanks for your quick response Sunil.

    It indeed helped to increase my understanding.

    But, further it is raising one more question in my mind about ECC checking.

    When i compared the RAM module of the TMS570LSx parts with the TMS570LCx, i found that some registers are missing in the TMS570LCx and there new memory scrubbing concept is added.

    And as per the reference manual of the TMS570LCx, in the 8.2.2.4 L2RAMW Error Types and Responses, section we can monitor the ESM module to get the error source. But, is it possible to

    get this errors without intervention of the EPC if i want to perform self tests on the RAM for the ECC single and multi bit correctable and uncorrectable errors?

    is there any code sequence for the TMS570LCx devices to test the RAM/Flash for these errors during selftest?

  • 0 in reply to Shivam Kakad
    TI__Mastermind 49120 points

    Please see the example included along with the Safety Diagnostics Library for how to implement checking of the ECC mechanism for Flash and RAM accesses.

    You can download the SDL from here: http://www.ti.com/tool/SAFETI_DIAG_LIB