Other Parts Discussed in Thread: HALCOGEN
Hello TI team,
I'm currently working on safety test implementation for TMS570LS0432 and faced one issue, which I can't explain. Hope you could help me with it.
In startup routine I have the following sequence implemented:
1. PBIST self-check (PBIST ROM + March13 Single-Port).
- Expected: Self-Check is expected to be failed.
- Actual: Self-Check is failed.
2. PBIST self-test (PBIST ROM + Triple Read Slow+Fast)
- Expected: Self-Test is expected to be passed.
- Actual: Self-Test is passed.
3. PBIST self-test (STC ROM + Triple Read Slow+Fast)
- Expected: Self-Test is expected to be passed.
- Actual: Self-Test is passed.
4. STC self-check (One interval, start from interval 0, SELF_CHECK_KEY = Ah, FAULT_INS = 1)
- Expected: Self-Check is expected to be failed after CPU reset.
- Actual: Self-Check is failed after CPU reset.
5. Reset all flags after STC self-check, incl. ESM
6. STC self-test (all intervals, start from interval 0, SELF_CHECK_KEY = 5h, FAULT_INS = 0)
- Expected: Self-Test is expected to be passed after CPU reset.
- Actual: Self-Test is failed after CPU reset (CPU1 = fail, CPU2 = fail, no timeout).
And the most interesting. If I change steps 2 and 3, everything works as expected (step 6 is finished with no failure).
Do you have any ideas what could be a reason?
MCU silicon rev.B is used, PBIST4 workaround is not valid, but I tried. It does not help.
Let me know please if any additional info is required.
Thanks in advance for your support,
Dmitry
P.S. In theory I could do PBIST ROM check after STC ROM check to have everything working, but quite strange why ROM check order has any influence of further test run.
Who knows what else influence it could has, maybe 'passed' test result is not valid.
