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Original question:

ESM1.90 - SYS - Register Soft Error

TMS570LC4357: Register Soft Error / Reaction on Multi-bit flip

Stephan HERMANNS
Intellectual 590 points
Part Number: TMS570LC4357


Dear Team of TI Hercules Support,

The common understanding of Soft Errors in High-Integrity Registers is that of single bit flips.

How about Multi-bit flips?

(Q1) Are they judged as very very unlikely, maybe because of architectural measures e.g. as bits which are distributed over the silicon?

(Q2) Are they signalled the same way as single-bit flips by ESM Group 1 Channels 88 to 91?
(Q3a) Is there a permanently running HW diagnostics detecting multi-bit flips?
(Q3b) Or are multi-bit flips only detected when the particular High Integrity Register is accessed, e.g. by SW?

Thank you in advance for your support - Happy afternoon!

Stephan

  • 0
    Intellectual 590 points

    Hi,

    There's an additional information in section 7.150 of the TMS570LC4357 safety manual /spnu540a/:

    "Double bit flips within these structures are flagged as an error and signaled through the ESM."

    This statement does not match my understanding of ESM Group 1 Channel 88 to 91 errors i got from posts in this forum.
    So which statement is correct?

    [ ] ESM Group 1 Channel 90 Errors arise from single bit flips in High Integrity bits insinde the (SYS) module
    [ ] ESM Group 1 Channel 90 Errors arise from double bit flips in High Integrity bits inside the (SYS) module

    Thank you

    Stephan

  • 0 in reply to Stephan HERMANNS
    TI__Mastermind 49120 points

    Hi Stephan,

    Each bit of these high-integrity register fields are actually implemented as a set of 5 flops. This implementation supports auto-correction for up to 2 bits of errors. If there are more than 2 errors within these 5 flops, then it is detected as an uncorrectable error and signaled to ESM channels 88 through 90.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Intellectual 590 points

    Hi, Sunil,

    Many thanks for your quick response and your precise answer!

    (Q5) Are Correctable Register Soft Errors (up to two bits flipped) corrected quietly and are not signaled in any way, not by ESM and not by setting a status bit?

    (Q6) Is there a difference between your answer and the statement in section 7.150 of the Safety manual almost at the bottom of page 77 of spnu540a.pdf
    "Double bit flips within these structures are flagged as an error and signaled through the ESM."?
    Maybe the latter should be read as "Double bit flips Uncorrectable errors within these structures are flagged as an error and signaled through the ESM?

    Thank you again

    Stephan

  • 0 in reply to Stephan HERMANNS
    TI__Mastermind 49120 points

    Hi Stephan,

    (Q5) Are Correctable Register Soft Errors (up to two bits flipped) corrected quietly and are not signaled in any way, not by ESM and not by setting a status bit?

    >> Yes, that is correct.

    (Q6) Is there a difference between your answer and the statement in section 7.150 of the Safety manual almost at the bottom of page 77 of spnu540a.pdf

    >> Yes, the description in the safety manual needs to be updated to match the actual implementation capability.

    Regards, Sunil