Experts,
During TMS570LC4357 bootup, occasionally , NERROR pin change from low->high->low->high, totally in 15us. Vcore voltage is 0.9V by then. After bootup, everything looks fine. Is it normal? and why?
thanks
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Experts,
During TMS570LC4357 bootup, occasionally , NERROR pin change from low->high->low->high, totally in 15us. Vcore voltage is 0.9V by then. After bootup, everything looks fine. Is it normal? and why?
thanks
Hi Ryan,
The nERROR has default pull (pull-down) enabled while nPORRST is low, and the pull is disabled immediately after nPORRST goes High.
If the nERROR pin has a external pull-up resistor, the nERROR pin is LOW until nPORRST is released.
low->high->low->high --> is not normal.
Yes, this will cause issues. Please make sure that datasheet requirements for nPORRST timings are followed strictly.
Regards, Sunil
Sunil,
some questions:
1. what will happen if nPORRST is driven high before core supply within the recommended operating range.
2. NERROR abnormal phenomenon is caused by item 1, right?
3. In picture 6.1 of datahsheet, it is said nPORRST need to drive low 2us after 1.2V voltage drop to below 1.14V. However, Chapter 6.3.2 said there is no power down sequence requirement. Could you comment on this? what will happen if power down sequence doesn't be met?
thanks
Ryan,
We cannot predict the behavior of the part if the core supply is not within the recommended operating range.
Picture 6.1 says that nPORRST must be driven 2us before core supply drops below 1.14V. Most system designers meet this requirement by tuning the core supply up (e.g. 1.26V nominal instead of 1.2V), and setting the low-threshold higher than 1.14V.
The section 6.3.2 says that there is no strict sequencing requirement between the core and I/O supplies. This still requires the nPORRST timing requirements to be strictly met.