TMS570LC4357: Can SRAM contents be corrupted by resets?

user6343383

Can SRAM contents be corrupted by resets other than power-on reset?

We want to guarantee that the contents of the SRAM will not be changed after a reset, because we want to use the information from before the reset.

In particular, I'm worried that if a reset occurs while writing to SRAM, the contents will be corrupted.

over 5 years ago

0 QJ Wang over 5 years ago

TI__Guru**** 199346 points

Hello,

We don't explicitly state/guarantee the content of the SRAM can be preserved after a reset cycle. You should treat the SRAM content as suspect for corruption after a reset cycle and take steps to validate the contents. You can not assume the device will ensure the contents are preserved even if it seems to act like it on the bench.

A warm reset can be due to various reset events such as OSC fail, watchdog reset, software reset and external reset. Software reset can be controlled by the CPU but others are not.

When a reset happens in the middle of a write operation to the SRAM, it can result in corruption of the SRAM contents as the timing protocol to the SRAM may not be met.

0 user6343383 over 5 years ago in reply to QJ Wang

Prodigy 80 points

Dear Mr. Wang,

Thank you for the advice. I understood. I will think other ways.

0 allen kitchen over 5 years ago in reply to user6343383

Intellectual 320 points

If you are wanting to save a state, so you can pick it up later...

Consider a small FRAM from Cypress. They are 8 pin packages and you use SPI to read and write. Writing 16 bytes is a simple matter of 17 bytes out on spi and then setting /CS again. Likewise reading. No waits for things to be stable or anything - very fast. You can write a state to the device using SPI hundreds of seconds for a century without any problem --Ferroelectric ram doesn't wear out.

CY15B004 for instance. (Wish TI had external FRAM parts.)