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TMS570LC4357: Question about diagnostic test of the L2RAMW redundant address decode logic and the compare logic

user5896989
Prodigy 220 points

Part Number: TMS570LC4357

Hello,
We want to use mechanism to test the operation of the redundant address decode logic and the compare logic (as described in the TRM)
We have this configuration:
- Clear all RAM status bit register (RAMERRSTATUS register)
- Set DIAG_DATA_VECTOR_H = 0x00000000 in DIAG_DATA_VECTOR_H and DIAG_DATA_VECTOR_L = 0x00000000
- Set DIAG_ECC = 0x0C
- In RAMADDRDEC_VECT register, set ECC Select Vector [DESV] =  ‘0x1’ and RAM chip select = 0xFFFF
- In RAMTEST, TEST_ENABLE = Ah  and write  TEST_MODE =  0x1 (INEQUALITY)
- Activate TRIGGER  to launch Selftest diagnostic mode
- Wait tests complete (Trigger bit set to ‘0’) (with a time-Out of 1 second)
In RAMERRSTATUS register, we read Bit MMDE (bit12) = 0 and bit ADDE (Bit 4) = 1
This is my question :
what is the expected value for "ADDE" Bit in Inequality test mode: '0' (An error did not occur) or '1' (An error occurred)?
Is it normal to have '1' or is there a problem with the configuration ?
Best regards, 
François
  • 0
    TI__Guru**** 200596 points

    Hello Francois,

    1. Inequality test mode: the XOR of two inputs should be 0xFF..FF. If the XOR is zero, error occurs -->ADDE is SET

    2. equality test mode: the XOR of the two inputs should be 0x00..00. If the XOR is not zero, error occurs -->ADDE is SET.

  • 0 in reply to QJ Wang
    Prodigy 220 points
    Hello Wang,
    Thank you for your answer.

    If I understand, decode and compare logic Diagnostic test must always return ADDE bit = '0' except if an HW problem with TMS is detected. Is it right?
    In my case, ADDE Bit is set, probably due to problem of test configuration (and not HW error): do you see something wrong in my test procedure?
    Best regards,
    François
  • 0 in reply to user5896989
    TI__Guru**** 200596 points

    Hi Francois,

    The ADDE bit is only used in test mode. In inequality test mode, ADDE bit should always be set (=1) except for HW problem in decode and compare logic.

    Your configuration is good. The ADDE=0x1 is an expected return value.