Compiler/TMS570LC4357: RAM Scrubbing

Hello Sho,

1. The memory scrubbing is enabled by setting teh MSE bit in RAMCTRL register. Since memory scrubbing uses the L2RAMW SECDED logic, the ECC Detect Enable (ECC_DETECT_EN) field in RAMCTRL must be enabled too.

2. To enhance device safety, the L2RAMW has a SECDED malfunction detection feature to ensure that the SECDED logic is functioning correctly. If the memory scrubbing is enabled, a single bit ECC error will be first detected by the L2RAMW and then corrected before written back to the memory. The corrected data later returned to the CPU will undergo another ECC checking which is done inside the CPU. 

EPC (error profiling controller) will record the single bit error address once the error is detected. A repeating error on the same address will not generate an error to the ESM since the error is already recorded. This is to prevent a repeating NMI interrupt to the CPU if you are in a loop. Please see below expert from the TRM (Page 486, SPNU563A):

The 64-bit aligned address of the correctable fault from each IP FIFO is sent to the CAM to check if the correctable fault is unique or repetitive. If it is a repetitive address for the correctable fault, then the correctable fault and its address are discarded and no further indication to the CPU. If it is a unique address, then the address will be remembered in the CAM content and CAM index will be set to occupied. It is software configurable to raise an error event to ESM if SERRENA bits in EPCCNTRL are enable.

Hello QJ Wang,

Thank you for reply.

I understood about RAM scrubbing configuration and EPC specification.

RAM scrubbing is only operated on L2RAMW, right?
in addition, if RAM scrubbing is completed at once, will the next begin immediately, or based on clock timing?

Sincerely yours,

Sho