TMS570LC4357: L2RAMW/L2FMC control and command parity

Hi Max,

Q1: What is the command parity and why is there only a „command parity error on idle“?

The CPU calculates a parity bit that includes the address and control signals. This parity bit is sent to the slave module that receives the transaction (Flash/ RAM), which then decodes this parity bit based on its own calculation based on the address and control signals. "IDLE" is the command defined in the OCP (on-chip networking protocol) when a bus master is not performing a read or a write to memory. A parity error during this command is treated separately and is captured in the RAM/Flash error status register as well as output to the ESM. The parity error on other commands is a separate signal (ESM 3.13 and 3.15).

Q2: Is the L2FMC „Mcmd parity error on Idle command“ the same as the L2RAMW „command parity error on idle“, but for the L2FMC?

Yes, that is correct.

Q3: Is the L2FMC „internal parity error“ the same as a control parity error?

The L2FMC block checks the parity on an incoming address from the CPU. It also keeps checking the parity for all "transfers" of this address information within the L2FMC sub-blocks. Any parity error detected during these internal transfers is also flagged as an address parity error (ESM 2.17).

Hope this helps.

Regards, Sunil

Hi Sunil,

Thank you for Clarifying! This helps alot.

Best Regards,

Max