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TM4C1294NCPDT: status of GPIO ports during Reset period

Part Number: TM4C1294NCPDT


  Hi,

  I am an analog design engineer with limited digital design practical experience. Recently, I have been involved in a project (together with other engineers in my group) that has TIVA uC in it. I have a question regarding behavior of TIVA GPIO ports while TIVA is in reset.

  I will be using one of the GPIO ports as an output at the input of a discrete logic circuit. I would like to know how this GPIO port will behave from the time the TIVA is reset until it comes out of reset so that I can predict the output of my discrete logic circuit accordingly. 

  I apologize if this info is readily available in TIVA's datsheet already. In this case, I would appreciate if someone can direct me to the relevant pages of the datasheet. Thanks.

  Ekrem. 

  • Once the power is good, the pins are in a high-impedance state with the pulls disabled until they are configured.

    It is on page 754 of the datasheet. (The datasheets are very large. No problem asking when you cannot find something.)

  • I guess, while the TIVA is in reset, this period is considered that power is good. I understand.

    I want to make sure I don't see any blip or glitch at a GPIO pin while TIVA is in reset or in configuration period. Otherwise a short blip or momentary glitch at this GPIO pin would send a wrong signal to my system supervisor messing up my system.

    Ekrem. 

  • The only thing to be careful of is as the voltage ramps up. I have seen small (500-600mV) glitches on I/O pins as the supply voltage transitions  through that range. Above about 700mV everything looks good.

  • The GPIO pins are said to power up as tri-state input.

    But you can tie the pin by using an external pull-up or -down resistor.

    When the controller comes on-line, it can easily manage the x-tra load, but you will be almost sure, where the pin is until then.