CCS/TMS570LS1224: Connecting TMS570LS1224 launchpad with microchip dspic33ev256GM106 starter kit via spi

from michrochip datasheet the MCU has two bit 

1)CKE: SPIx Clock Edge Select bit

1 = Serial output data changes on transition from active clock state to Idle clock state 

0 = Serial output data changes on transition from Idle clock state to active clock state

2)CKP: Clock Polarity Select bit

1 = Idle state for clock is a high level; active state is a low level

0 = Idle state for clock is a low level; active state is a high level

so what do you think how to configure hercules to be compatible with it .

do i need to write CSHOLD =false;  ?  also in halcougen config i set polarity 0 , phase 0.

this is my HAL settings 

could you have a look to my spi master code

/* USER CODE END */

/* Include Files */

#include "sys_common.h"

/* USER CODE BEGIN (1) */
#include "spi.h"
/* USER CODE END */

/* USER CODE BEGIN (2) */
uint16 TX_Data_Master[16] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10 };
/* USER CODE END */

int main(void)
{
/* USER CODE BEGIN (3) */
    spiDAT1_t dataconfig1_t;

    dataconfig1_t.CS_HOLD = FALSE;
    dataconfig1_t.WDEL    = TRUE;
    dataconfig1_t.DFSEL   = SPI_FMT_0;
    dataconfig1_t.CSNR    = 0xFE;


    /* Enable CPU Interrupt through CPSR */
    _enable_IRQ();

    /* Initialize SPI Module Based on GUI configuration
     * SPI1 - Master ( SIMO, SOMI, CLK, CS0 )
     * SPI3 - Slave  ( SIMO, SOMI, CLK, CS0 )
     * */
    spiInit();





    while(1){

        /* Initiate SPI1 Transmit through polling Mode */
        spiTransmitData(spiREG1, &dataconfig1_t, 16, TX_Data_Master);
    }
/* USER CODE END */

    return 0;
}

/* USER CODE BEGIN (4) */
/* USER CODE END */

gentle reminder

Hello,

What clock edge and clock polarity do you select for dspic33? If dspic33 requires de-assertion of chip select between two transfer, you need to set CSHOLD=FALSE.

Also microchip has this bit 

SMP: SPIx Data Input Sample Phase bit

Master mode: 1 = Input data is sampled at the end of data output time 0 = Input data is sampled at the middle of data output time

Slave mode: The SMP bit must be cleared when the SPIx module is used in Slave mode.

Clock edge = 0. and polarity =0.  and SMP = 0. In microchip

Phase =0. Polarity= 0 in hercules

Did you get problem with your current settings?

It's better to set clockedge=1 (falling edge), please try it first.

I Sent word array of 0xAAAA,0X5555 (16 bit set in halcogen with phase 0 and polarity 0) baudrate of 1000khz

i received in slave buffer  0x4848,0x0484. (16 bit ,SMP 0 and polarity 0,clock edge 1)

CS_Hold (( slave side )The slave select  pin must stay asserted for the entire 16 bit transfer.) If  slave isn't directly using the slave select signal itself, apart from enabling its use by the peripheral, then it does not matter what SS does between transfers.

/* USER CODE END */

/* Include Files */

#include "sys_common.h"

/* USER CODE BEGIN (1) */
#include "spi.h"

/* USER CODE END */
/* USER CODE BEGIN (2) */
//uint16 TX_Data_Master[16] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10 };
uint16 TX_Data_Master[2] = { 0xAAAA,0x5555};
/* USER CODE END */

int main(void)
{
/* USER CODE BEGIN (3) */
    spiDAT1_t dataconfig1_t;

    // The chip select signal is held continuously active during several consecutive data word transfers
    dataconfig1_t.CS_HOLD = FALSE;
    /* After a transaction, WDELAY of the corresponding data format will be loaded into the delay counter.
     No transaction will be performed until the WDELAY counter overflows. The SPISCS pins will be deactivated
     for at least (WDELAY + 2) * VCLK_Period duration. */
    dataconfig1_t.WDEL    = FALSE;
    // Data word format 0 is selected
    dataconfig1_t.DFSEL   = SPI_FMT_0;
    // Chip select number. CSNR defines the chip-select that will be activated during the data transfer (0 in our case).
    dataconfig1_t.CSNR    = 0xFE;


    /* Enable CPU Interrupt through CPSR */
 //   _enable_IRQ();

    /* Initialize SPI Module Based on GUI configuration
     * SPI1 - Master ( SIMO, SOMI, CLK, CS0 )
     * SPI3 - Slave  ( SIMO, SOMI, CLK, CS0 )
     * */
    spiInit();


    while(1)

    {
        /* Initiate SPI1 Transmit through polling Mode */
        spiTransmitData(spiREG1, &dataconfig1_t, 2, TX_Data_Master);

      //  __delay_cycles(1000);
    }
/* USER CODE END */

    return 0;
}

/* USER CODE BEGIN (4) */
/* USER CODE END */

Have you tried clock edge 0? Is the data sent correctly on SPI data bus?

For TMS570 SPI clock mode with polarity=0 and phase=0, the data is output on the rising edge of SPICLK, and the input data is latched on the falling edge of the SPICLK. So I expect that the input data on salve side is latched on the rising edge of SPICLK. 

it works now thanks so much.

i want now to make hercules as slave do i write the code correctly  

* ------------------
* GUI configurations
* ------------------
* 1) Driver TAB
* - Select SPI1
* 2) VIm Channel 0-31
* - Enable MIBSPI1high  & MIBSPI1low channels.
* 3) PINMUX enable MIBSPI1
* -disable conflict MIBSPI1SOMI_1 on pin 105
* 4) SPI1 TAB
* - SPI1 Global SubTAB
* - Uncheck Master Mode
* - Uncheck Internal Clock

* - enable RXINT (high level)

5)SPI1 Data format 

 -baudrate 1Mhz, 16 bit,polarity 0 ,phase 0,

6)SPI1 port 

-enable SIMO0,SOMI0,CLK,CS[0]

#include "sys_common.h"

#include "spi.h"



uint16 RX_Data_Slave[16]  = { 0 };


int main(void)
{

    spiDAT1_t dataconfig1_t;

    dataconfig1_t.CS_HOLD = FALSE;
    dataconfig1_t.WDEL    = FALSE;
    dataconfig1_t.DFSEL   = SPI_FMT_0;
    dataconfig1_t.CSNR    = 0xFE;

    _enable_IRQ();


    spiInit();


    spiGetData(spiREG1, &dataconfig1_t, 4, RX_Data_Slave);

    while(1);


    return 0;
}