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RM46L852: SPI Active High Chip Select

Part Number: RM46L852
Other Parts Discussed in Thread: HALCOGEN

Hello,

I am attempting to use the SPI interface with an active high chip select. The Tech. Ref. Manual (SPNU514C) states:

 

27.2.3.1 Multiple Chip Selects

The SPICS pins that are used must be configured as functional pins in the SPIPC0 register. The default

pattern to be put on the SPICS when all the slaves are deactivated is set in the SPIDEF register. This

pattern allows different slaves with different chip-select polarity to be activated by the SPI.

The master-mode SPI is capable of driving either 0 or 1 as the active value for any SPICS output pin. The

drive state for the SPICS pins is controlled by the CSNR field of SPIDAT1. The pattern that is driven will

select the slave to which the transmission is dedicated.

Given this it should be possible to choose an active high chip select when in master mode.

I can get the transaction working properly with the standard active low chip select, in master mode. I have tried changing the CSDEF field in the SPIDEF register. When setting that whole register or the 0th bit to 0 the chip select is always low. This still follows the tech ref because the CSDEF description is "SPICS is cleared to 0 when no transfer is active". Therefore it is zero when no transfer is active but still active low so always zero.

I do not see any other registers, or settings in HALCoGen, to change to enable active high chip select however that one paragraph seems to indicate it is possible. I am using HALCoGen to generate all my drivers for SPI. The CSDEF field needed to be set outside of the HALCoGen code because this was not a setting in HALCoGen.

Any help will be appreciated.

Thank you,

Tom

  • Hi Tom,

    During SPI data transmission, the value in CSNR of SPIDAT1 is driven on SPINCS pin. When the transmission finishes, the default CS value defined by CSDEF is put on SPINCS.

    To use CS active HIGH for 1 SPI slave device, the bit of CSDEF should be "0", and the corresponding bit in CSNR should be "1". For chip select 0: CSDEF=0xFE, and CSNR=0x01.

    HALCOGen GUI doesn't contain this selection for SPI compatible mode. You need to add CSDEF configuration code manually.

  • Works great.


    Thanks for clearing that up.

    -Tom