Part Number: TMS570LS0432
Other Parts Discussed in Thread: HALCOGEN
Tool/software: Code Composer Studio
Hello,
I've written code to detect a single edge-driven interrupt on GIOA[1], having configured gio.c using HALCoGen in the usual fashion. No other interrupt vectors are configured.
The setup is that the interrupt vector, gioHighLevelInterrupt, is correctly used to set the Program Counter upon interrupt, and a breakpoint placed at the first { bracket of the gioHighLevelInterrupt routine will cause CCS7 to stop the execution here. However, clicking Step Into, the next instruction, uint32 offset = gioREG->OFF1; is entirely ignored, with the PC jumping to sys_intvecs.asm >> undefEntry where it hangs.
I believe that this error handler is visited if there is more than one interrupt which has not correctly exited. I've tried everything I can think of regarding register/priority/flag setting/clearing (using the Memory Browser), whether before I cause an interrupt (from a venerable HP single-shot pulse generator), or having paused at the breakpoint and then changing the register settings. If the interrupt enable bit is not set, I correctly don't see any interrupt...
I use the command "_enable_IRQ();" to allow global interrupts after gio configuration. In accordance with SPNU517C para 14.2.2, bit 7 of CPSR is set once the interrupt breakpoint is reached. So, when running cleanly, CPSR = 0x400035F. After interrupt, CPSR = 0x40003D2. Once the undefEntry hang is reached, CPSR = 0x400003DB.
Any help welcome, Thanks.