SPI Slave Mode CS\ Timing Requirement

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Regards,

Haixiao

Hi Haixiao,

I am also interested in the slave timing reqiurements for SPIDELAY fields C2TDELAY and T2CDELAY when in 3-pin mode, running at both 4MHz and 8MHz. Do you have any requirements/recommendations for these timings yet?

Regards, Tony.

1. These two parameters are only applicable to master mode. In my mind, C2TDELAY is very important in 4 pin (with cs) mode. For example, if you talk one TMS570 to another TMS570 device in 4 pin mode, usually, you need to set the C2TDELAY. Otherwise, you might miss the first bit that you try to transfer. The background around this is: SPICS is 2mA pin, and SPICLK is 4mA pin, therefore, the SPICLK delay from master to slave is shorter than SPICS. If the SPICLK arrives before (even at the same time) SPICS arrives, one single bit is missing.

2. These two parameters should not be applicable to 3 pin mode. I am not 100% sure since have not looked into the VHDL file. But based on an experiment  I did, in the same configuration, in 4pin mode, I have to set C2TDELAY to grantee the signal integrity, but in 3 pin mode, not data bit is missing even if I don’t do that. 

Regards,

Haixiao

Hi Haixiao,

Typographical mistake from me, I am using 4-pin mode (with CS), not 3-pin mode.

I have found, as you suggest, that some C2TDELAY is essential. I have two TMS570 linked over SPI running at 8MHz. The borderline time for C2TDELAY seems to be 75ns. Below this value, the first bit transmitted by the slave is not present, above this value, data from the slave is received without loss. I have set T2CDELAY to zero as I can see no reason for a delay.

I am interested to know if TI have recommended settings for C2TDELAY and T2CDELAY for TMS570 interconnections? I think this was the intent of Anthony's original post.

Regards, Tony.