Other Parts Discussed in Thread: HALCOGEN
Tool/software: Code Composer Studio
Dear All,
i faced some problem about mibspi Driver and DMA on Task.
all code is based on example code of HALCOGEN.
Main code is below. last configuration for DMA is done with HALCOGEN (like TransGroup0 ,and size...and others
What i want to do is i wantuse mibspi driver with DMA on Task which is PRIVILEGE Mode.
Thanks
/** @file HL_sys_main.c
#include "HL_sys_common.h"
#include "FreeRTOS.h"
#include "os_task.h"
#include "HL_mibspi.h"
#include "HL_sys_dma.h"
#define D_SIZE1 128
#define SYSTASK 0
#define USERTASK 1
void loadDataPattern_mcp(uint32 psize, uint16* pptr);
void loadDataPattern_mcp_0(uint32 psize, uint16* pptr);
void mibspiEnableInternalLoopback_mcp(mibspiBASE_t *mibspi);
void dmaConfigCtrlPacket_mcp(uint32 sadd,uint32 dadd,uint32 dsize);
void mibspiDmaConfig_mcp(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel);
#pragma SET_DATA_SECTION(".sharedRAM")
uint16 TXDATA_mcp[D_SIZE1]; /* transmit buffer in sys ram */
uint16 RXDATA_mcp[D_SIZE1]= {0}; /* receive buffer in sys ram */
#pragma SET_DATA_SECTION()
int cnt_mibspi;
static portSTACK_TYPE stackbuffer[configMINIMAL_STACK_SIZE] __attribute__ ((aligned (configMINIMAL_STACK_SIZE * sizeof(portSTACK_TYPE))));
/* Define Task Handles */
xTaskHandle xTask1Handle;
xTaskHandle xTask2Handle;
/* Task1 */
void vTask1(void *pvParameters)
{
for(;;)
{
/* Taggle HET[1] with timer tick */
vTaskDelay(100);
}
}
/* Task1 */
void vTask2(void *pvParameters)
{
loadDataPattern_mcp_0(D_SIZE1,&TXDATA_mcp[0]);
/* - initializing mibspi - enabling tg 0 , length 127 (halcogen file)*/
mibspiInit();
/* - enabling loopback ( this is to emulate data transfer without external wires */
mibspiEnableLoopback(mibspiREG4,Digital_Lbk);
#if USERTASK
g_dmaCTRL g_dmaCTRLPKT3_task, g_dmaCTRLPKT4_task; /* dma control packet configuration stack */
/* - configuring dma control packets */
g_dmaCTRLPKT3_task.SADD = (uint32)TXDATA_mcp; /* source address */
g_dmaCTRLPKT3_task.DADD = (uint32)&(mibspiRAM4->tx[0].data); /* destination address */
g_dmaCTRLPKT3_task.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT3_task.FRCNT = 1; /* frame count */
g_dmaCTRLPKT3_task.ELCNT = D_SIZE1; /* element count */
g_dmaCTRLPKT3_task.ELDOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT3_task.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT3_task.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT3_task.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT3_task.PORTASGN = PORTA_READ_PORTB_WRITE;
g_dmaCTRLPKT3_task.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT3_task.WRSIZE = ACCESS_16_BIT; /* write s
g_dmaCTRLPKT3_task.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT3_task.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT3_task.ADDMODEWR = ADDR_OFFSET; /* address mode write */
g_dmaCTRLPKT3_task.AUTOINIT = AUTOINIT_ON; /* autoinit */
g_dmaCTRLPKT4_task.SADD = (uint32)&(mibspiRAM4->rx[0].data); /* source address */
g_dmaCTRLPKT4_task.DADD = (uint32)RXDATA_mcp; /* destination address */
g_dmaCTRLPKT4_task.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT4_task.FRCNT = 1; /* frame count */
g_dmaCTRLPKT4_task.ELCNT = D_SIZE1; /* element count */
g_dmaCTRLPKT4_task.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT4_task.ELSOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT4_task.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT4_task.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT4_task.PORTASGN = PORTB_READ_PORTA_WRITE;
g_dmaCTRLPKT4_task.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT4_task.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT4_task.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT4_task.ADDMODERD = ADDR_OFFSET; /* address mode read */
g_dmaCTRLPKT4_task.ADDMODEWR = ADDR_INC1; /* address mode write */
g_dmaCTRLPKT4_task.AUTOINIT = AUTOINIT_ON; /* autoinit */
dmaReqAssign(DMA_CH2,DMA_REQ37 );
dmaReqAssign(DMA_CH3,DMA_REQ36);
/* - setting dma control packets */
dmaSetCtrlPacket(DMA_CH2,g_dmaCTRLPKT4_task);
dmaSetCtrlPacket(DMA_CH3,g_dmaCTRLPKT3_task);
/* - setting the dma channel to trigger on h/w request */
dmaSetChEnable(DMA_CH2, DMA_HW);
dmaSetChEnable(DMA_CH3, DMA_HW);
/* - configuring the mibspi dma , channel 0 , tx line -0 , rxline -1 */
/* - refer to the device data sheet dma request source for mibspi tx/rx */
/* setting transmit and receive channels */
mibspiREG4->DMACTRL[0] |= (((6<<4)|7) << 16);
/* enabling transmit and receive dma */
mibspiREG4->DMACTRL[0] |= 0x8000C000;
/* setting Initial Count of DMA transfers and the buffer utilized for DMA transfer */
mibspiREG4->DMACTRL[0] |= (0 << 8) |(127<<24);
dmaEnable();
/* - start the mibspi transfer tg 0 */
mibspiTransfer(mibspiREG4,0 );
/* - configuring the mibspi dma , channel 0 , tx line -0 , rxline -1 */
/* - refer to the device data sheet dma request source for mibspi tx/rx */
while(!(mibspiIsTransferComplete(mibspiREG4,0)))
{
};
while(1)
{
vTaskDelay(100);
loadDataPattern_mcp_0(D_SIZE1,&TXDATA_mcp[0]);
/* setting transmit and receive channels */
mibspiREG4->DMACTRL[0] |= (((6<<4)|7) << 16);
/* enabling transmit and receive dma */
mibspiREG4->DMACTRL[0] |= 0x8000C000;
/* setting Initial Count of DMA transfers and the buffer utilized for DMA transfer */
mibspiREG4->DMACTRL[0] |= (0 << 8) |(127<<24);
/* - start the mibspi transfer tg 0 */
mibspiTransfer(mibspiREG4,0 );
while(!(mibspiIsTransferComplete(mibspiREG4,0)))
{
};
#if 0
PrintNoPrefix("TXDATA_mcp: \n\r");
int cnt;
for (cnt = 0; cnt < 128; cnt++)
{
if ((cnt % 16) == 0) PrintNoPrefix("\n\r");
PrintNoPrefix("0x%02x ", TXDATA_mcp[cnt]);
}
PrintNoPrefix("\n\r");
PrintNoPrefix("RXDATA_mcp: \n\r");
for (cnt = 0; cnt < 128; cnt++)
{
if ((cnt % 16) == 0) PrintNoPrefix("\n\r");
PrintNoPrefix("0x%02x ", RXDATA_mcp[cnt]);
}
PrintNoPrefix("\n\r");
#endif
}
#endif
}
/* USER CODE END */
/*Task 1 Parameters*/
static const xTaskParameters xTaskParamters2={
vTask2, /* Function that implements the task */
(const signed char *)"Blinky",/* Just a text name for the task to assist debugging */
configMINIMAL_STACK_SIZE, /* Stack size */
NULL, /* Parametrs to be passed to the task function */
(1|portPRIVILEGE_BIT), /* Task Priority. set the portPRIVILEGE_BIT (1|portPRIVILEGE_BIT) if the task should run in a privileged state*/
stackbuffer, /* Buffer to be used as the task stack */
/* xRegions - Allocate up to three separate memory regions for access by the task, with appropriate access permissions.*/
/* No region is set in this example. */
/* Note: OS configures Full RAM region as type portMPU_NORMAL_OIWBWA_NONSHARED. Users must be careful while setting any RAM region with a different type */
{ /* Base address Length Parameters (Permission | Type) */
{0,0,0}, /* { cReadWriteArray, 32, portMPU_REGION_READ_WRITE | portMPU_NORMAL_OIWBWA_NONSHARED }, */
{0,0,0}, /* { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY | portMPU_NORMAL_OIWBWA_NONSHARED }, */
{0,0,0} /* { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE | portMPU_NORMAL_OIWBWA_NONSHARED }*/
}
};
/* USER CODE BEGIN (2) */
/* USER CODE END */
void main(void)
{
/* USER CODE BEGIN (3) */
cnt_mibspi =100;
#if 1
#if SYSTASK
cnt_mibspi =100;
loadDataPattern_mcp_0(D_SIZE1,&TXDATA_mcp[0]);
/* - initializing mibspi - enabling tg 0 , length 127 (halcogen file)*/
mibspiInit();
/* - enabling loopback ( this is to emulate data transfer without external wires */
mibspiEnableLoopback(mibspiREG4,Digital_Lbk);
g_dmaCTRL g_dmaCTRLPKT3_mcp, g_dmaCTRLPKT4_mcp; /* dma control packet configuration stack */
/* - configuring dma control packets */
g_dmaCTRLPKT3_mcp.SADD = (uint32)TXDATA_mcp; /* source address */
g_dmaCTRLPKT3_mcp.DADD = (uint32)&(mibspiRAM4->tx[0].data); /* destination address */
g_dmaCTRLPKT3_mcp.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT3_mcp.FRCNT = 1; /* frame count */
g_dmaCTRLPKT3_mcp.ELCNT = D_SIZE1; /* element count */
g_dmaCTRLPKT3_mcp.ELDOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT3_mcp.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT3_mcp.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT3_mcp.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT3_mcp.PORTASGN = PORTA_READ_PORTB_WRITE;
g_dmaCTRLPKT3_mcp.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT3_mcp.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT3_mcp.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT3_mcp.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT3_mcp.ADDMODEWR = ADDR_OFFSET; /* address mode write */
g_dmaCTRLPKT3_mcp.AUTOINIT = AUTOINIT_ON; /* autoinit */
g_dmaCTRLPKT4_mcp.SADD = (uint32)&(mibspiRAM4->rx[0].data); /* source address */
g_dmaCTRLPKT4_mcp.DADD = (uint32)RXDATA_mcp; /* destination address */
g_dmaCTRLPKT4_mcp.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT4_mcp.FRCNT = 1; /* frame count */
g_dmaCTRLPKT4_mcp.ELCNT = D_SIZE1; /* element count */
g_dmaCTRLPKT4_mcp.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT4_mcp.ELSOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT4_mcp.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT4_mcp.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT4_mcp.PORTASGN = PORTB_READ_PORTA_WRITE;
g_dmaCTRLPKT4_mcp.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT4_mcp.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT4_mcp.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT4_mcp.ADDMODERD = ADDR_OFFSET; /* address mode read */
g_dmaCTRLPKT4_mcp.ADDMODEWR = ADDR_INC1; /* address mode write */
g_dmaCTRLPKT4_mcp.AUTOINIT = AUTOINIT_ON; /* autoinit */
dmaReqAssign(DMA_CH2,DMA_REQ37 );
dmaReqAssign(DMA_CH3,DMA_REQ36);
/* - setting dma control packets */
dmaSetCtrlPacket(DMA_CH2,g_dmaCTRLPKT4_mcp);
dmaSetCtrlPacket(DMA_CH3,g_dmaCTRLPKT3_mcp);
/* - setting the dma channel to trigger on h/w request */
dmaSetChEnable(DMA_CH2, DMA_HW);
dmaSetChEnable(DMA_CH3, DMA_HW);
/* - configuring the mibspi dma , channel 0 , tx line -0 , rxline -1 */
/* - refer to the device data sheet dma request source for mibspi tx/rx */
mibspiDmaConfig_mcp(mibspiREG4,0,6,7);
dmaEnable();
/* - start the mibspi transfer tg 0 */
mibspiTransfer(mibspiREG4,0 );
/* - configuring the mibspi dma , channel 0 , tx line -0 , rxline -1 */
/* - refer to the device data sheet dma request source for mibspi tx/rx */
while(1)
{
loadDataPattern_mcp_0(D_SIZE1,&TXDATA_mcp[0]);
mibspiDmaConfig_mcp(mibspiREG4,0,6,7);
/* - start the mibspi transfer tg 0 */
mibspiTransfer(mibspiREG4,0 );
while(!(mibspiIsTransferComplete(mibspiREG4,0)))
{
};
//while(dmaGetInterruptStatus(DMA_CH4, BTC) != TRUE);
// while(dmaGetInterruptStatus(DMA_CH3, FTC) != TRUE);
// while(dmaGetInterruptStatus(DMA_CH4, FTC) != TRUE);
/* loop forever */
#if 0
PrintNoPrefix("TXDATA_mcp: \n\r");
int cnt;
for (cnt = 0; cnt < 128; cnt++)
{
if ((cnt % 16) == 0) PrintNoPrefix("\n\r");
PrintNoPrefix("0x%02x ", TXDATA_mcp[cnt]);
}
PrintNoPrefix("\n\r");
PrintNoPrefix("RXDATA_mcp: \n\r");
for (cnt = 0; cnt < 128; cnt++)
{
if ((cnt % 16) == 0) PrintNoPrefix("\n\r");
PrintNoPrefix("0x%02x ", RXDATA_mcp[cnt]);
}
PrintNoPrefix("\n\r");
#endif
};
#endif
/* - configuring the mibspi dma , channel 0 , tx line -0 , rxline -1 */
/* - refer to the device data sheet dma request source for mibspi tx/rx */
#endif
/* Create Task 1 */
if (xTaskCreate(vTask1,"Task1", configMINIMAL_STACK_SIZE, NULL, 1, &xTask1Handle) != pdTRUE)
{
/* Task could not be created */
while(1);
}
/* Create Task 2 */
if (xTaskCreateRestricted(&xTaskParamters2, &xTask2Handle) != pdTRUE)
{
/* Task could not be created */
while(1);
}
/* Start Scheduler */
vTaskStartScheduler();
/* Run forever */
while(1);
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
/** void mibspiEnableLoopback(mibspiBASE_t *mibspi )
*
* enabling internal loopback on mibspix
*/
#if 1
void mibspiEnableInternalLoopback_mcp(mibspiBASE_t *mibspi )
{
/* enabling internal loopback */
mibspi->GCR1 |= 1U << 16U;
}
/** void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)
*
* configuring mibspi dma with
*
* channel > mibspi dma channel number
* txchannel > transmit channel dedicated for mibspi
* rxchannel > receive channel dedicated for mibspi
*/
void mibspiDmaConfig_mcp(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)
{
uint32 bufid = D_SIZE1 - 1;
uint32 icount = 0;
/* setting transmit and receive channels */
mibspi->DMACTRL[channel] |= (((rxchannel<<4)|txchannel) << 16);
/* enabling transmit and receive dma */
mibspi->DMACTRL[channel] |= 0x8000C000;
/* setting Initial Count of DMA transfers and the buffer utilized for DMA transfer */
mibspi->DMACTRL[channel] |= (icount << 8) |(bufid<<24);
}
/** void loadDataPattern(uint32 psize, uint16* pptr)
*
* loading a randam data chunk into system ram
*
* pptr > sys ram address
* psize > chunkl size
*
*/
void loadDataPattern_mcp(uint32 psize, uint16* pptr)
{
int i;
for(i=0;i<psize;i++)
{
TXDATA_mcp[i] = i+3;
}
}
void loadDataPattern_mcp_0(uint32 psize, uint16* pptr)
{
int i;
for(i=0;i<psize;i++)
{
TXDATA_mcp[i] = cnt_mibspi;
}
cnt_mibspi++;
}
#endif
/* USER CODE END */
