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TMS570LC4357: Errors injection in VIM RAM

Adama
Intellectual 310 points
Part Number: TMS570LC4357


Hello,

The following steps are done by my software to generate a single-bit Error (SBE) in VIM RAM :

  1. Read a data in VIM RAM (address 0xFFF82090)
  2. Disable ECC management (ECCENA=0x5, ECCCTL = 0x05050A05)
  3. Flip bit0 of the data read then, write it back in VIM RAM
  4. Enable ECC (ECCENA=0xA, ECCCTL = 0x05050A0A)
  5. Read the VIM data to generate the single-bit error (SBE)

It is observed that SBE = 1 (OK) but also UERR = 1 (ECCSTAT = 0x00000101) and software local variables are reseted.

Can you explain why UERR is also set in this case and why local variables have been damaged ?

Best Regards,

  • 0
    TI__Guru**** 198766 points

    Hell Adama,

    To test the ECC checking mechanism in VIM RAM, the ECC bits allows manual insertion of faults. This option is implemented using the TEST_DIAG_EN bit in the ECCCTL register control bit. Once TEST_DIAG_EN is enabled, the ECC bits are mapped to 0xFFF82400. In this mode, the user can modify the ECC bits without changing the data bits. Can you try to flip ECC bit instead of flipping data bit?

    Flipping one data bit may impact 2 or more ECC bit.