Hello,
We want to test ECC VIM RAM mechanism by corrupting single bit in the Data as described in TRM p.675
"The following sequence should be used for injecting faults to data bits and testing the ECC check feature.
1. Write the data locations of VIM RAM with the required patterns while keeping ECCENA active. The
ECC bits will be automatically initialized along with data bits.
2. Disable ECC by setting ECCENA=0 in ECCCTRL register. In this mode, writing to data bits does not
automatically update ECC bits.
3. In this mode, it is possible to corrupt data bits using any of the following methods.
• Read the data bits, flip one bit and write back
4. Depending on the kind corruption created, read back the data bits and check for the correction error
(single-bit error or double-bit error or no error ).
5. Read the UERRADDR and SBERRADDR registers and check for the correct address capture as well"
When we try this procedure, Single bit error on Data is not corrected and SBER bit = 0'.
1st question:
Between step 3 and 4, we think there's an error in TRM, ECC_ENA must be activated to verify that SBER bit is correcty setting with 1 bit in error. Can you confirm it?
2nd question:
When we activate ECC_ENA bit register (between step 3 and 4), Single bit error and Double bit errors are detected (SBER bit = 1 and UERR bit = 1).
We don't understand why UERR bit setting? According to TRM when we corrupt only 1 bit in Data, it's only single-bit error mechanism which works and not both. Can you confirm it?
3th question:
Do you have an example of test by corrupting 1 Data bit and 2 Data bits on VIM RAM area?
Best regards,
François
