Reading data received on the SCI interface.

Looks like the baud rate is wrong. Can you publish your PLL register values and your SCI init routine?

Regards,

Haixiao

Haixiao,

thanks for the quick reply.  Below are the sciInit routine and PLL values:

Is your suggestion that the processor's baud speed is incorrect?

Maybe I should retuurn to setting baud rate register explicitly with sciREG1->BAUD = 325;?

Regards,

Steve


void sciInit(void)
{
    /** @b intalise SCI1 @b */

    /** - bring SCI out of reset */
    sciREG1->GCR0 = 1U;

    /** - Disable all interrupts */
    sciREG1->CLRINT    = 0xFFFFFFFF;
    sciREG1->CLRINTLVL = 0xFFFFFFFF;

    /** - global control 1 */
    sciREG1->GCR1 = (1 << 25)  /* enable transmit */
                  | (1 << 24)  /* enable receive */
                  | (0 << 10)  /* Disable multi buffer mode */
                  | (1 << 5)   /* internal clock (device has no clock pin) */
                  | ((1-1) << 4)  /* number of stop bits */
                  | (1 << 3)  /* even parity, otherwise odd */
                  | (0 << 2)  /* no parity */
                  | (1 << 1);  /* asynchronous timing mode */    

    /** - set baudrate */
    //sciREG1->BAUD = 325;  /* baudrate */  // SN - this is 9600 bits/sec see p 539 of manual
    
    // SKCN
    sciSetBaudrate(sciREG1, 9600);  // SN set baud rate indirectly

    /** - tranmision length */
    sciREG1->LENGTH = 7;  /* length */
    
    /** - set SCI pins functional mode */
    sciREG1->FUN = (1 << 2)  /* tx pin */
                 | (1 << 1)  /* rx pin */
                 | (0);  /* clk pin */

    /** - set SCI pins default output value */
    sciREG1->DOUT = (0 << 2)  /* tx pin */
                  | (0 << 1)  /* rx pin */
                  | (0);  /* clk pin */

    /** - set SCI pins output direction */
    sciREG1->DIR = (0 << 2)  /* tx pin */
                 | (0 << 1)  /* rx pin */
                 | (0);  /* clk pin */

    /** - set SCI pins open drain enable */
    sciREG1->ODR = (0 << 2)  /* tx pin */
                 | (0 << 1)  /* rx pin */
                 | (0);  /* clk pin */

    /** - set SCI pins pullup/pulldown enable */
    sciREG1->PD = (0 << 2)  /* tx pin */
                | (0 << 1)  /* rx pin */
                | (0);  /* clk pin */

    /** - set SCI pins pullup/pulldown select */
    sciREG1->PSL = (1 << 2)  /* tx pin */
                 | (1 << 1)  /* rx pin */
                 | (1);  /* clk pin */

    /** - set interrupt level */
    sciREG1->SETINTLVL = (0 << 26)  /* Framing error */
                       | (0 << 25)  /* Overrun error */
                       | (0 << 24)  /* Pariry error */
                       | (0 << 9)  /* Receive */
                       | (0 << 8)  /* Transmit */
                       | (0 << 1)  /* Wakeup */
                       | (0);  /* Break detect */

    /** - clear interrupt flags */
    sciREG1->FLR = 0xFFFFFFFF;

    /** - set interrupt enable */
    sciREG1->SETINT = (0 << 26)  /* Framing error */
                    | (0 << 25)  /* Overrun error */
                    | (0 << 24)  /* Pariry error */
                    | (1 << 9)  /* Receive */
                    | (0 << 8)  /* Transmit */
                    | (0 << 1)  /* Wakeup */
                    | (0);  /* Break detect */

    /** - inialise global transfer variables */
    g_sciTransfer[0].length = 0;

    /** - Finaly start SCI1 */
    sciREG1->GCR1 |= (1 << 7);
}


PLL register values:

  U:\Workspaces\TMS570 Safety MCU Demos\Demo_Software_Ver1_1\src\system.h (18 hits)
    Line 43: *     - Pll
    Line 48: *     - Flexray Pll
    Line 55:     SYS_PLL      = 1, /**< Alias for Pll clock Source                       */
    Line 55:     SYS_PLL      = 1, /**< Alias for Pll clock Source                       */
    Line 60:     SYS_FR_PLL   = 6, /**< Alias for flexray pll clock Source               */
    Line 60:     SYS_FR_PLL   = 6, /**< Alias for flexray pll clock Source               */
    Line 70: *     - Pll
    Line 75: *     - Flexray Pll
    Line 77: #define PRE1 SYS_PLL
    Line 85: *     - Pll
    Line 90: *     - Flexray Pll
    Line 92: #define PRE2 SYS_PLL
    Line 111:     unsigned SSWPLL1;                /* 0x0024 */
    Line 112:     unsigned SSWPLL2;                /* 0x0028 */
    Line 113:     unsigned SSWPLL3;                /* 0x002C */
    Line 130:     unsigned PLLCTL1;                /* 0x0070 */
    Line 131:     unsigned PLLCTL2;                /* 0x0074 */
    Line 199:     unsigned PLLCTL3;        /* 0x0000 */

  Opps forgot to add:

U:\Workspaces\TMS570 Safety MCU Demos\Demo_Software_Ver1_1\src\system.c (14 hits)
    Line 61:     /** @b Initialize @b Pll: */
    Line 63:     /** - Setup pll control register 1:
    Line 65:     *     - Setup bypass on pll slip
    Line 66:     *     - Setup Pll output clock divider
    Line 69:     *     - Setup Pll multiplier         
    Line 71:     // Workaround for FMZPLL#17 errata
    Line 72:     SYSTEM_1->PLLCTL1 = 0x41036300U;
    Line 73:     SYSTEM_1->PLLCTL1 = 0x21036300U; // Prathap 100 MHZ from 16MHZ
    Line 78:     /** - Setup pll control register 1
    Line 82:     *     - Setup internal Pll output divider
    Line 85:     SYSTEM_1->PLLCTL2 = 0x3FC0623DU;
    Line 103:     SYSTEM_1->GHVSRC = (SYS_PLL << 24U)
    Line 104:                      | (SYS_PLL << 16U)
    Line 105:                      |  SYS_PLL;

The baud rate in page 325 is specified for VCLK =50MHz. In your case, could you please connect the device with CCS4, find out the register value at 0xffffff70 and 0xffffff74 and 0xffffffd0?

They are the PLL register value and HCLK to VCLK ratio.

Thanks,

Haixiao

Sorry I misunderstood you, here are register values:

Normal 0 false false false EN-GB X-NONE X-NONE MicrosoftInternetExplorer4 0xffffff70    21036300

0xffffff74    3FC0623D

0xffffffd      00000100

Steve

Haixiao,

just to let you know for sure the above register vales are when using:

sciREG1->BAUD = 325;

not;

sciSetBaudrate(sciREG1, 9600);

Steve

OK, I'll give it a go, maybe 18 hrs before I get back to you (end og day here).

To be certain, can I change 0xFFFFFFD0 on the fly, i.e. if I change it in CCS will the change take effect?

should I be using:

Normal 0 false false false EN-GB X-NONE X-NONE MicrosoftInternetExplorer4

sciREG1->BAUD = 325;

or

sciSetBaudrate(sciREG1, 9600);

or does it not matter.

Regards Steve

I don't know what is in function sciSetBaudrate.

But the final goal is to write the sciREG1 register.

You can change 0xFFFFFFD0 in the Fly to see if it works. After that change, disconnect and connect  the Hyper terminal. In your code, you can set it before you init your PLL.

Regards,

Haixiao

Morning Haixiao,

Making the change on the fly seems not to work.

So, have break point at:

    VIM_PARITY->PARCTL = 0xA; in system.c

At which point I set 0xFFFFFFD0 to 0x01010100

I am now getting:

Hyperterminal    TMS570

*  (0x42)                  ª (0xAA)

1 (0x31)                 ± (0xB1)

2 (0x32)                ² (0xB2)

.....

All the values are too large by 128.  i.e. the eight bit is set.  From reading the manaul I'd assume the eight bit should be zero, but this is not the case.

I am not doing any bit shifting of the data read form the sciREG1->RD buffer, although this would not help.

Looks like I'm nearly there, any further ideas?

Regards,

Steve

Haixio,

It is working!

Had an error in the hypeterminal settings data bits should be 8 not 7 to match the setting of:

sciREG1->LENGTH = 7;  /* length */

where 7 means the response field has 8 bytes/characters.

Am not bit shifting since all 8 bits are used.

Have break point at:

    VIM_PARITY->PARCTL = 0xA; in system.c

At which point I set 0xFFFFFFD0 to 0x01010100

I am looking in to the setting of the baud rate correctly i.e. by setting 0xFFFFFFD0 to 0x01010100 during setting using the PLL registers.

Can you give any guidence on that at all?

Thanks for you help,

Steve