CCS/TMS570LC4357: Low Power Mode - How? Where can I get more documentation?

Hello Chris,

This is an example of how t enter the three low power modes:

There are several bus masters on this device: CPU, DMA, DMM, EMAC, FTU, HTU, POM.. Thise are listed in Table 4-1 of SPNU563A (TRM).

Thanks for pointing me to the example code.

Some issues, there were some variables that didn't exist and I replaced what was in their place. 

For example, FPAC2 doesn't exist in flashWREG, but the same value (from the comments) matches up to rsvd5.

flashWREG->rsvd5 /*FPAC2*/ = 0x7;

Another example:

flashWREG->FBPWRMODE /*FBFALLBACK doesn't exist in current HalCoGen code for TMS570LC4357*/

Initial problem, the code crashes on this line:

/* Disable oscillator monitoring to prevent detection of osc fail */
systemREG1->CLKTEST = 0x010A0000;

Invalid value for TMS570LC4357?

Hi Chris, 

I will check, then come back to you.

QJ - Any luck?

Is there any examples for putting the TMS570LC4357 into a low-power state (sleep, doze, etc.) and waking it up?

Hello,

1. uint32 FBPWRMODE;       /* 0x0040 */ is declared in the flash header file generated by HALCoGen

2.  FPAC2 is not listed in the TRM. FPAC2 is at address offset of 0x4C.

To enter low power mode (Doze, Snooze, Sleep), the 4th step is required. Application needs to write to the clock domain disable register (CDDIS) to disable the GCLK1/2 (CPU clock), HCLK1/2 (system clock), VCLKP (peripheral VBUS clock), VCLK2/3 (peripheral VBUS clock), and VCLKA1/2/4 (asynchronous peripheral VBUS clock). All these domains must be disabled in order to be considered in doze /snooze/sleep mode. The RTICLK domain may or may not be disabled. Doze/Snooze modes are normally used in conjunction with an RTI in order to wake up the device periodically from within.

You enabled the range detection (24th bit), but you disabled the range detection circuitry (25th bit).. 

The example you gave, https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/435025, is the Sleep/Doze/Snooze code it uses, valid for TMS570LC4357?

I changed bit 25 to enabled

systemREG1->CLKTEST = 0x30A0000;

The code is still jumping to

prefetchEntry
        b   prefetchEntry

The example code is for RM46 device. The procedure in the example code does apply to TMS570LC43x as well.

When did you call systemREG1->CLKTEST = 0x30A0000? Is the OSC clock valid when you set CLKTEST register?

I'm not sure the OSC clock is set. Going from the example, it's difficult to tell what was set in HalCogen as it doesn't highlight the changes that were made from the default values (which would be VERY helpful).

Here is the main:

     boolean switchA;

     while (1)
     {
         //command = gioGetPort(gioPORTA) & 0x3;       // read GIOA[1:0] port status

         switchA = gioGetBit(gioPORTB, 4);

         //if (command == 0x00)
         if (switchA != 0)
         {
             /* stay active */

             // Reset the GIOB6 pin
             gioSetBit(gioPORTB, 6, 0);
         }
         else
         {
             // On pressing User Switch A, it is pulled down to ground
             // Set the GIOB6 pin
             gioSetBit(gioPORTB, 6, 1);

             /* Setup the flash banks and pump active grace periods as 7 HCLK/16 cycles*/
             flashWREG->rsvd5 /*FPAC2*/ = 0x7;

             /* Bank 7 */
             flashWREG->FMAC = 0x6;
             flashWREG->FBAC = 0x70F;

             /* Bank 0 */
             flashWREG->FMAC = 0x0;
             flashWREG->FBAC = 0x70F;

             /* Setup flash module to change fallback modes for banks/pump to be "sleep" */
             flashWREG->FBPWRMODE /*FBFALLBACK*/ = 0x00000000U
                                   | (uint32)((uint32)SYS_SLEEP << 14U) /* BANK 7 */
                                   | (uint32)((uint32)SYS_SLEEP << 2U)  /* BANK 1 */
                                   | (uint32)((uint32)SYS_SLEEP << 0U); /* BANK 0 */

             /* Disable oscillator monitoring to prevent detection of osc fail */
             // This register should only be used for test and debug purposes.??
//             systemREG1->CLKTEST = 0x010A0000; // from RM46 - doesn't work

             systemREG1->CLKTEST = 0x30A0000;

             enter_doze();

             //post_wakeup();
         }

QJ - any luck with this?

Hi Chris,

I am sorry for late response. 

The L2FMC on LC4357 is different from the FMC used on other Cortex-R4F devices. The L2FMC doesn't have BAGP (bank active grace period) and PAGP. (Pump active grace period). When the PUMP power mode is switched to SLEEP mode (by clearing PUMPPWR bit in FPAC1 register), the L2FMC will immediately apply the new power mode to the PUMP. When the BANK1, BANK2 and BANK7 power mode is switched to a mode other than ACTIVE mode (FBPWRMODE register), the L2FMC will immediately apply the new power mode to the affected banks. This means that the following code for disabling clock source and clock domain need to be executed from SRAM.

This is the reason that running "systemREG1->CLKTEST = 0x30A0000;" from flash causes abort.

Do you have a sample project for TMS570LC4357 -- to enter a low power state (i.g. doze)?

Hello Chris,

I don't a sample project. I wrote a example code to sleep the flash pump and flash banks:

void Flash_Sleep(void)
{
     /* Flash Bank Access Control Register (FBAC) */
     flashWREG->FBAC = (0x00 << 16) //OTP programming is disabled
                                        |(0x0F); //VREAD setup for wakeup
     flashWREG->FBPWRMODE = (0x0 << 14) | (0x00); //Take Bank 0 and 1, and 7 to sleep mode
     flashWREG->FPAC1 = (0x01F << 16) //PSleep: for wakeup
                                         | 0x0;                //Take Pump to Sleep
}