hello!
we can get the nERROR Pin Timing in the section 12.2.2 of the TMS570LS3137 TRM manual. Now I'm confused about the example 6.
the example 6 describes this"
"
Q1: "There now is a scenario where the ERROR pin is high and the group2/3 status flag is set. " Is the scenario unreasonable ? how do I understand this in module levell and chip level?
Q2:If there are many faliures occurred,such as five. What should the application do in right way ? What is the expected nERROR Pin scenario?