TMS570LS3137: nERROR Pin Timing example 6

Susan Yang

Part Number: TMS570LS3137

Dear team

I saw 12.2.2 ERROR Pin Timing in the following document

I feel confusion with Example 6. Could anyone show me a Figure like Figure 12-8. ERROR Pin Timing - Example 5?

If there are more than two failures, how should the application handle these failures?
what is the expected phenomenon of nERROR Pin?

Please help

0 QJ Wang over 5 years ago

Hi Susan,

1. If there is no nERROR reset request, the nERROR pin is kept LOW.

2. If there is nERROR reset request, and the 2nd error occurs before the nERROR goes back to HIGH, the nERROR LOW time counter will be extended.

In this case, the TRM recommends to force the nERROR high before the 2nd error occurs.

0 Susan Yang over 5 years ago in reply to QJ Wang

Thanks for your reply.

Please help to fix the following link (same customer)

0 QJ Wang over 5 years ago in reply to Susan Yang

I have answered that thread.

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