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TMS570LC4357: Impact of the DMA on the CPU

Tom Wid
Prodigy 60 points
Part Number: TMS570LC4357

Hello,

I have several questions regarding the TMS570LC4357 and the DMA:

1. What is the impact of DMA transfer on the core? Can the DMA block the core from executing in some cases?

2. What are the priorities for memory access, is the core higher priority than DMA?

3. Is it possible to calculate the worst case for DMA transfer time? If yes, how to calculate it?

Thanks!

Tomasz

  • 0
    TI__Guru**** 197036 points

    Hello Tom,

    The CPU SRAM interconnect is designed such that an arbitration condition only exists if both the CPU and the DMA are accessing the same 64-bit address in the same cycle. In that rare case of the CPU and DMA (or other bus master) access the same 64-bit SRAM location in the same cycle, the read access will be delayed by one CPU clock cycle to allow the write access to complete first.

    The DMA controller does provide several interrupt conditions that can be used to by the CPU: Frame Transfer Completed, Last Frame Transfer Started, Half Block Transfer Completed, and Block Transfer Completed.

    You can use PMU to calculate the time used by DMA transfer

  • 0 in reply to QJ Wang
    Prodigy 60 points

    What will happen if there are two writes (from both DMA and CPU) on the same 64bit address? And what if there are two reads?

  • 0 in reply to Tom Wid
    TI__Guru**** 197036 points

    Hi,

    The CPU interconnect uses rotating priority scheme. Rotating priority is based on a round-robin scheme.