TMS570 CAN Interrupt

Your request has been forwarded to the DCAN expert.

Regards,

Haixiao

Himanshu,

Let me know the following :

1. Is it that you are not getting any  interrupts or just the CAN receive interrupts.

2. So are you able to see and confirm the received CAN messages in the message box ?

Best Regards,

Pratip

Pratip,

We are looking to get receive interrupts to work.

Right now, we have working code that increments a number between 0 and 63, sends the number over CAN, receives it, and sets the NHET port to that number so that the LEDs will display the current value. This is done through using a counter interrupt and loop back.

We have been trying to write similar code that uses a second interrupt to write the value to the NHET port when the message gets received, but we are having trouble.

regards

Hi Himansu,

So does this mean you are able to see the received incremental data in the message RAM ? Atleast the first one ?

Also try using IF3 registers , there is a receive update flag which is easier to poll.

I need to know your CAN register settings or I can try to provide with an example settings that I have for your referance.

Best regards,

Pratip

Pratip,

Thanks.

Can you please provide me with the example code you have mentioned.

I will get back to you on your other  questions.

regards

Pratip,

Yes, we can get the incremented numbers from the messagebox. This works fine. It's just getting the interrupts to trigger that is eluding us.

The CAN settings that we are  using right now are fairly arbitrary, we are just trying to test out the chip to see if we want to use it. So the example should be fine.

regards

Himanshu,

Refer the attached files.8358.DCAN23.c

Best Regards

Pratip2766.DCAN23.c6558.DCAN22.c

Pratip,

Would it be possible to get the header files referenced in these examples?

Thanks

regards

0363.test_can.zipHimanshu,

Find attached the header files.

You may have to first analize and narrow down the issue to VIM settings or the CAN settings.

Try to look into the dcan1_config() routine for CAN settings.

Best Regards,

Pratip

Pratip,

Thanks for this - we figured out what was going on - it works now. Thanks for your help.

regards

Himansu,

Thats good news!!!

Was it within the CAN or at system level ?

Keep going....

Regards,

Pratip

hi Pratip,

Yes, I am trying to send a message from CAN1 and receive from CAN2.

I have connected a device that links the CAN L and H ports with the PC.

David

Hi David,

In your debugger window, can you verify if your bit 7 of CPSR is 0? If it is set to 1, your global IRQ interrupts are disabled. If you manually clear this bit and run your code, adding swi_enable_irq will solve your problem. This function enables your CPU IRQ interrupt. 

swi_enable_irq();

IRQMASK .equ  0x80

_swi_enable_irq

bic r1, r1, #IRQMASK

msr spsr_cxsf, r1

VIM module has three modes to handle interrupts. VIM RAM allows you to preload the base addresses of your exceptions. This init is needed if you use vectored interrupt mode. Additional details can be found in device TRM.

VIM_RAM_Init();

B Chavali

Hi B Chavali,

I checked the bit 7 of CPSR and it is 1 (if the first one it is bit 0) . CPSR=60000393.

I have tried to add swi_enable_irq function, for example in the file sys_core.asm, but an error appears all the time.

[E0002] Ilegal mnemonic specified

I have also tried to put the initialization program of the device TRM:

IRQENABLE .equ 0x80

_Enable_Irq

MRS R1, CPSR

BIC R1, R1, #IRQENABLE

MSR CPSR, R1

MOV PC, LR

but after some modifications (insted of MSR-> msr, CPSR->spsr_cxsf...) the same error appears.

[E0002] Ilegal mnemonic specified

Is the function OK?

David 

David,

If you manually enable the bit 7 of CPSR, are you getting your interrupts?

Which tool chain are you using to compile your code? TI tools recognize spsr_cxsf. This is following ARM standard. I am enclosing sample asm file that shows the function declaration and definition. In your asm file, are you indenting your above code. Some tools use column 0 and need code to start after column 0.

2148.sys_svc.asm 

B Chavali

hi B Chavali,

thanks for your help, but this doesn´t work yet... I´m using de CCS v4.1.1.00014 .

I had tried with your svc.asm file, I haven´t any compiling problems, but when I inserted the swi_enable_irq() function in my main program it didn´t recognize the function.

I tried to declare the function "extern void __swi_enable_irq(void);" but nothing.

If I don´t called in the main program to the function the CPSR register still the same CPSR= 0x60000393.

David

Hi David,

Software interrupt requires swi instruction execution. Instantiating swi_enable_irq is creating a C function call. CCS compiler has SWI_ALIAS pragma that dispatches this SWI function.

These details can be found in spnu151f document. This document can be found at http://focus.ti.com/lit/ug/spnu151f/spnu151f.pdf - section 5.9.14

When you generate SWI interrupt, you can pass a number to differentiate between multiple tasks. If you have one task, you can ignore this argument. You need to add this function to your project.

Sample project found on tms570 contains all these files.

B Chavali7462.swi_util.h

Hi,

I forgot adding the header file swi_util.h on my main program,  now it recognize swi_enable_irq() function and the bit 7 of the CPSR register is 0.

But the program still doesn´t work!!

Can you please provide me an email to send my program and look for what I´m doing wrong?

Thanks,

David