TMS570LS3137: TMS570LS3137: Using SYSESR and RTIWDSTATUS after startup

Hello,

I have a question about SYSESR register and WDRST bit.

I need information in application code when microcontroller is reseted by DWWD time out. I am using bootloader and startup code generated by Halcogen. Part of the function _c_int00() is below.

Information if reset is caused by DWWD is cleared in startup procedure (line 16) so I can't use this information in application code. But the EXTRST bit which is also set in case of DWWD timeout is not cleared. Also RTIWDSTATUS is not changed in startup routine, so using these two information I can determine if reset is caused by DWWD.

Is this safe way to handle DWWD resets?

Second question is can I check watchdog violation by examining WDRST bit elsewhere in the code, after all tests are performed?

If I comment out code where WDRST is cleared (line 16) then my application never starts (even bootloader is not starting) and it seems function afterSTC() (line 53) never execute.

void _c_int00(void)
{
    // Enable EventBusExport, FlashEcc and some errata here ...

    if ((SYS_EXCEPTION & POWERON_RESET) != 0U)      /* SYSESR */
    {
        SYS_EXCEPTION = 0xFFFFU;/* clear all reset status flags */
    }
    else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
    {
    }
    else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
    {
        if(WATCHDOG_STATUS != 0U)
        {
            SYS_EXCEPTION = WATCHDOG_RESET;
        }
        else
        {
            SYS_EXCEPTION = ICEPICK_RESET;
        }
    }
    else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
    {
        SYS_EXCEPTION = CPU_RESET;
        
        /* check if this was an stcSelfCheck run */
        if ((stcREG->STCSCSCR & 0xFU) == 0xAU)              /* Signature compare logic self-check enable key */
        {
            if ((stcREG->STCGSTAT & 0x3U) != 0x3U)
            {
                stcSelfCheckFail();             /* STC self-check has failed */           
            }
            else                                /* STC self-check has passed */          
            {
                stcREG->STCSCSCR = 0x05U;       /* clear self-check mode */            
                stcREG->STCGSTAT = 0x3U;        /* clear STC global status flags */           
                esmREG->SR1[0U] = 0x08000000U;  /* clear ESM group1 channel 27 status flag */       
                
                cpuSelfTest(STC_INTERVAL, STC_MAX_TIMEOUT, TRUE);                            
            }
        }
        else if ((stcREG->STCGSTAT & 0x1U) == 0x1U)         /* Self-test run completed. */
        {
            if ((stcREG->STCGSTAT & 0x2U) == 0x2U)        /* Test Fail */
            {
                cpuSelfTestFail();                    
            }
            else         /* CPU self-test completed successfully */                               
            {
                stcREG->STCGSTAT = 0x1U;  
                
                afterSTC();                                
            }
        }
        else                                        /* CPU reset caused by software writing to CPU RESET bit */
        {
        }
    }
    else if ((SYS_EXCEPTION & SW_RESET) != 0U)      /* Reset caused due to software reset.*/
    {
    }
    else                                            /* Reset caused by nRST being driven low externally.*/
    {
    }


    // Check for ESM group 3 errors, initialize System - Clock, Flash settings with Efuse self check, 
    // run a diagnostic check on the memory self-test controller, 
    // run and check PBIST on STC ROM, 
    // run and check PBIST on PBIST ROM, run stcSelfCheck

    // ....
}