TMS570LC4357: Very slow programming /flashing

Last attempt - 2:06.35.   (Over 2 mins ! what a pain )

Process:

CortexR5: GEL Output: Memory Map Setup for Flash @ Address 0x0
CortexR5: GEL Output: Memory Map Setup for Flash @ Address 0x0 due to System Reset
CortexR5: Writing Flash @ Address 0x00000000 of Length 0x00000020
CortexR5: Erasing Flash Bank 0, Sector 0
CortexR5: Verifying Flash @ Address 0x00000000 of length 0x00000020
CortexR5: Writing Flash @ Address 0x00000080 of Length 0x00007ff0
CortexR5: Erasing Flash Bank 0, Sector 1
CortexR5: Erasing Flash Bank 0, Sector 2
CortexR5: Verifying Flash @ Address 0x00000080 of Length 0x00007FF0
CortexR5: Writing Flash @ Address 0x00008070 of Length 0x0000065c
CortexR5: Verifying Flash @ Address 0x00008070 of Length 0x0000065C
CortexR5: Writing Flash @ Address 0x00010000 of Length 0x00007ff0
CortexR5: Erasing Flash Bank 0, Sector 4
CortexR5: Erasing Flash Bank 0, Sector 5
CortexR5: Verifying Flash @ Address 0x00010000 of Length 0x00007FF0
CortexR5: Writing Flash @ Address 0x00017ff0 of Length 0x000075f0
CortexR5: Erasing Flash Bank 0, Sector 6
CortexR5: Verifying Flash @ Address 0x00017FF0 of Length 0x000075F0
CortexR5: GEL Output: Memory Map Setup for Flash @ Address 0x0 due to System Reset

Ready at main after that .

Hello,

The on board emulator is xds100v2. The maximum speed of xds100v2 is 1MHz. 

Please refer to table 6-31 of datasheet about the flash erase/program time:

The sector erase time is 0.3s~4s

The wide word (288 bit, flash bank width) programming time is: 40us~300us

Thanks QJ Wang , for the datasheet facts.

But could you offer / share debug config for CCSv10 , for this board, which works good for you?

Because clearly something wrong in my setup where I do not get proper communication with the target, and/or debug probe, or both.   

Here is that output from "Verify" debug probe connection output from CCS General  / Connection -> TI XDS100v2 USB Debug probe. 

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]

-----[Print the board config pathname(s)]------------------------------------

/home/esembdev/.ti/ccs1010/0/0/BrdDat/testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'libjioserdesusb.so'.
The library build date was 'May 7 2020'.
The library build time was '20:44:54'.
The library package version is '9.2.0.00002'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End]

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