TMS570LC4357: Dual Lock Step CPUs using same bus

Hello QJ Wang,

Thanks for the reply. Is this information present in any reference/safety manual? The data from any released document will prove to be a better evidence for my analysis.

In addition to shared bus usage, please confirm if any of the following is applicable to TMS570LC4357;

• more than one Central Processing Unit (CPU) are embedded and they use the same bus (which is not strictly separated or which uses the same single port memory)
• several controllers of complex peripherals are dependent on each other and exchange data
• several internal busses are integrated and are used in a dynamic way (for example, a dynamic bus switch matrix)

Regards, Infant Jesuraj 

Hello Infant,

The section 13.1 of TRM says that " All transactions between the lockstep CPUs and the rest of the system should only go through the main CPU."

Hello QJ Wang,

Thank you. 

Can you please confirm if any of the following is true for TMS570LC4357;

• more than one Central Processing Unit (CPU) are embedded and they use the same bus (which is not strictly separated or which uses the same single port memory)
• several controllers of complex peripherals are dependent on each other and exchange data
• several internal busses are integrated and are used in a dynamic way (for example, a dynamic bus switch matrix)

Regards, Infant Jesuraj

Hello QJ Wang,

For the third point "several internal busses are integrated and are used in a dynamic way (for example, a dynamic bus switch matrix)", can you please point me the reference/safety manual for evidence.

Thank You, Infant Jesuraj

Hello QJ Wang,

Can you please update on my last query?

Thanks, Infant Jesuraj