Part Number: TMS570LS0432
Tool/software: Code Composer Studio
Hello
I see the When TPS65381 RESET ,the VDDX=RAMPING, if that, is the ram of cpu clear? Is it hot start or cold start
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Part Number: TMS570LS0432
Tool/software: Code Composer Studio
Hello
I see the When TPS65381 RESET ,the VDDX=RAMPING, if that, is the ram of cpu clear? Is it hot start or cold start
If reset_cnt is a global variable in MCU, and if nRES is connected to nPORRST of MCU, the content in RAM including reset_cnt will be cleared
Hello
Is there any flash, power off start the data is cleared, but the watchdog restart the data is not cleared
The CPU reset is caused by the CPU self-test controller (LBIST). VMON and WatchDos are not the source of the CPU reset.
The data on flash is not affected by the the PORRST.
This device has SRAM INIT feature which clears all the SRAM. In system_startup.c, the memory init is called after watchdog reset, the RAM should be cleared too.